Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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36518518, G11C 1606

Patent

active

060814535

ABSTRACT:
A nonvolatile semiconductor memory device includes a memory cell having a drain electrically connected to a bit line, a source, a floating gate, and a control gate electrically connected to a word line, a sense amplifier for comparing a plurality of predetermined reference voltages with the bit line voltage to detect data stored in the memory cell and outputting one of first, second, and third outputs, and a logic circuit for determining stored data of two bits on the basis of the logic calculation of the first, second, and third outputs. It is determined whether desired data has been written, based on data read out in a verify-read operation after a write operation, at a time later than that for outputting readout data in a read operation. With this arrangement, the difference in read rate between selected memory cells can be minimized.

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