Static information storage and retrieval – Floating gate – Particular connection
Patent
1998-12-24
2000-11-07
Zarabian, A.
Static information storage and retrieval
Floating gate
Particular connection
36518523, G11C 1134
Patent
active
061445827
ABSTRACT:
A nonvolatile semiconductor memory device includes a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of 0V or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode. A source-to-drain current path of the first P-channel MOS transistor is connected in parallel to the source-to-drain current path of the first N-channel MOS transistor, and a source-to-drain current path of the second P-channel MOS transistor is connected in parallel to the source-to-drain current path of the second N-channel MOS transistor.
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Umezawa et al., "A 5-V-Only Operation 0.6.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, pp. 1540-1545, Nov. 1992.
Atsumi Shigeru
Banba Hironori
Kabushiki Kaisha Toshiba
Zarabian A.
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