Nonvolatile semiconductor memory device

Static information storage and retrieval – Addressing – Byte or page addressing

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Details

36523003, 365185, G11C 700

Patent

active

052933504

ABSTRACT:
A nonvolatile semiconductor memory device having a page program mode of operation. The device including a data input buffer for receiving program data from a data line and a plurality of program voltage generating circuits each of which is selectively operable for generating a program voltage output having a first and second logic level. The device further including a plurality of first selecting MOS transistors coupled to respective ones of the program voltage generating circuits and alternating ones of bit lines included in the memory device and a plurality of second selecting MOS transistors coupled to respective ones of the program voltage generating circuits and a second sequences of alternating one of the bit lines. A select circuit having a first output connected to each of the first selecting transistors and a second output connected to each of the second selecting transistors for selectively turning on either of the first and second selecting transistors to thereby selectively couple either the bit lines of the first and second sequence to the program voltage output of the respective ones of the program voltage generating circuits.

REFERENCES:
patent: 4878203 (1989-10-01), Arakawa
patent: 5065364 (1991-11-01), Atwood et al.

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