Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

1991-06-10

1994-09-13

Wambach, Margaret R.

Static information storage and retrieval

Read/write circuit

Sipo/piso

365185, G11C 1134

Patent

active

053474902

ABSTRACT:
Disclosed is a flash EEPROM including a voltage lowering circuit therein for lowering an externally applied high voltage serving as a source of an erase pulse to a predetermined voltage in a range in which a tunnel phenomenon sufficiently occurs in memory cells. The voltage lowered by the voltage lowering circuit is converted into a pulse of a small width, and the converted pulse is then applied as an erase pulse to the memory cells. A flash EEPROM including a memory cell array divided into first and second blocks is also disclosed. An erase pulse applying circuit for applying the voltage lowered by the voltage lowering circuit as an erase pulse to the memory cells, and an erase verify circuit for erase verifying are provided for each of the first and second blocks. The erase pulse applying circuit and the erase verify circuit corresponding to the first block and the ones corresponding to the second block are configured to operate independently.

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ISSCC 90/Wednesday, Feb. 14, 1990/Imperial Ballroom/2:30 p.m. "Non-Volatile and Fast Static Memories" Seki et al.
Subbreakdown Drain Leakage Current in MOSFET Chen et al. IEEE Electron Device Letters EDL-8, No. 11, Nov. 1987 pp. 515-517.
A Flash-Erase EEPROM Cell with an Asymmetric Source and Drain Structure, Kune et al. Central Research Laboratory, Hitachi IEEE/IEDM 1987 pp. 560-563.

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