Nonvolatile semiconductor memory device

Static information storage and retrieval – Read/write circuit – Particular read circuit

Reexamination Certificate

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Details

C365S148000, C365S158000, C365S171000, C365S173000, C365S185230

Reexamination Certificate

active

07606086

ABSTRACT:
A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells are arranged in a row and column direction, a circuit for applying a first voltage to a selected bit line, a circuit for applying a second voltage to unselected bit lines and word lines, a circuit for reading a current flowing in a selected memory cell, a voltage suppressor circuit for suppressing fluctuation of the second voltage with respect to each word line and bit line provided in the circuit for applying the second voltage, and a second voltage control circuit for applying the first voltage to the selected bit line and a dummy second voltage to the unselected bit lines and the word lines during the preset period and controlling the voltage suppressor circuit during a reading period so that the second voltage may fluctuate in a fluctuation direction of the first voltage.

REFERENCES:
patent: 6259644 (2001-07-01), Tran et al.
patent: 6836422 (2004-12-01), Perner et al.
patent: 6970387 (2005-11-01), Smith et al.
patent: 2005/0169038 (2005-08-01), Inoue et al.
patent: 2005/0276091 (2005-12-01), Inoue
patent: 2005/0276138 (2005-12-01), Inoue
patent: 2005-93049 (2005-04-01), None
patent: 2005-251378 (2005-09-01), None
patent: 2006-4479 (2006-01-01), None

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