Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-03-28
2006-03-28
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189040
Reexamination Certificate
active
07020028
ABSTRACT:
An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.
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Kubota Yasurou
Kume Hitoshi
Muto Tadashi
Seki Koichi
Shoji Kazuyoshi
Antonelli, Terry Stout and Kraus, LLP.
Hitachi ULSI Systems Co. Ltd.
Nguyen Van-Thu
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