Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2004-01-29

2004-12-21

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S325000, C257S366000, C257S411000

Reexamination Certificate

active

06833582

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and more particularly to a highly reliable nonvolatile semiconductor memory device that enables low voltage fast programming.
BACKGROUND OF THE INVENTION
MNOS (Metal-Nitride-Oxide-Semiconductor) memories and MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) memories are typical examples of nonvolatile memories (nonvolatile semiconductor memory devices) having storage nodes formed with insulator films. An MNOS memory is structured as a laminated layer comprising a conductive gate electrode layer (M), a silicon nitride film (N), a silicon oxide film (O), and a semiconductor substrate (S). An MNOS memory is structured as a laminated layer comprising a conductive gate electrode layer (M), a silicon oxide film (O), a silicon nitride film (N), a silicon oxide film (O) and a semiconductor substrate (S). In each of those MNOS and MONOS memories, carrier electrons are injected/ejected in/from a silicon nitride film provided with a charge trapping function to store/erase information therein/therefrom.
The structures of the above-described nonvolatile memories and the programming methods for them are disclosed in the patent document 1 (the official gazette of JP-A No. 102466/2001 (corresponding to U.S. Pat. No. 6,255,166)), the patent document 2 (the official gazette of JP-A No. 148434/2001 (corresponding to U.S. Pat. No. 6,388,293)), and the patent document 3 (corresponding to the official gazette of U.S. Pat. No. 5,969,383)
Hereunder, a brief description will be made for both structure and operation of a memory cell of the type disclosed in the patent document 1 (the official gazette of JP-A No. 102466/2001 (corresponding U.S. Pat. No. 6,255,166) and the patent document 2 (the official gazette of JP-A No. 148434/2001) with reference to FIG.
7
.
This nonvolatile memory cell is configured by two MOS transistors: a memory MOS transistor used as a storage block and a select MOS transistor used to select the memory block to read information therefrom. The select MOS transistor diffusion layer (source region)
607
B is connected to a common line while the select gate electrode
603
is connected to a select-word line. On the other hand, the memory MOS transistor diffusion layer (drain region)
607
A is connected to a bit line while the memory gate electrode
605
is connected to a memory word line.
The memory MOS transistor gate capacitor insulator film
604
is formed with a three-layer film, for example, comprising a silicon oxide film (the first layer film)
604
a
, a silicon nitride film (the second layer film)
604
b
, and a silicon oxide film (the third layer)
604
c
formed sequentially on the surface of the silicon substrate
661
. Each film thickness is as follows; the first layer
604
a
is about 3 to 4 nm, the second layer
604
b
is 10 nm and under, and the third layer
604
c
is about 2 to 4 nm.
The silicon nitride film formed as the second layer
604
b
of the memory MOS transistor is actually a charge trapping insulator film (layer) provided with a charge, trapping function. The silicon nitride film traps carrier electrons on the trapping levels formed in the silicone nitride film and at each interface between the silicone nitride film and its upper film and between the silicon nitride film and its lower film. The charge trapping film may be any of a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, etc. The first layer
604
a
and the third layer
604
c
are actually potential barrier films, for example, silicon oxide films and/or silicon oxynitride films.
To write information in this nonvolatile memory cell, a predetermined voltage is applied to the diffusion layer (source region)
607
B and the gate electrode
603
of the select MOS transistor to turn on the select MOS transistor and a predetermined voltage is applied to the diffusion layer (drain region)
607
A and the gate electrode
605
of the memory MOS transistor. At this time, some of the carrier electrons existing on the surface of the silicon substrate are injected into the gate capacitor insulator
604
due to the gate electrical field of the memory MOS transistor. The injected carrier electrons pass through the potential barrier of the silicon oxide film
604
a
(the first layer) to be trapped in the silicon nitride film (the second layer).
Information is erased from the nonvolatile memory cell in two ways. In one way, carrier electrons are ejected from the silicon nitride film
604
b
formed as a charge trapping film of the memory MOS transistor towards the silicon substrate
601
through the silicon oxide film
604
a
formed as a potential barrier film formed beneath the film
604
b
. In the other way, carrier electrons are ejected to the gate electrode
605
of the memory MOS transistor through the silicon oxide film
604
c
formed as the third layer. Both of the methods apply a voltage to the gate electrode
605
of the memory MOS transistor to eject the carrier electrons from the silicon nitride film
604
b
to erase information from the nonvolatile memory cell. The latter method can erase information from the nonvolatile memory cell with use of the same polarity as that used in the write operation has; an advantage that the circuit configuration is simplified; thereby the chip area is reduced.
To read information from the nonvolatile memory cell, it is checked first whether or not a predetermined current flows in the select MOS transistor according to the state of the threshold voltage of the memory MOS transistor when the select MOS transistor is turned on. Stored information is read from the memory cell when the current flows in the transistor.
Next, a brief description will be made for both structure and operation of a memory cell of the type disclosed in the patent document 3 (the official gazette of U.S. Pat. No. 5,969,383) with reference to FIG.
8
.
This nonvolatile memory cell is also configured by two MOS transistors; a memory MOS transistor that forms a storage block and a select MOS transistor used to select the memory block to read information therefrom. The select MOS transistor diffusion layer (source region)
707
B is connected to a common line while the, select gate electrode
703
is connected to a select-word line. On the other hand, the memory MOS transistor diffusion layer (drain region)
707
A is connected to a bit line while the memory gate; electrode
705
is connected to a memory word line.
The memory MOS transistor gate capacitor insulator film
704
is formed as a three-layer film. For example, it consists of a silicon oxide film (the first layer film)
704
a
, a silicon nitride film (the second layer film)
704
b
, and a silicon oxide film (the third layer film)
704
c
formed sequentially on the surface of a silicon substrate
701
. Each film thickness is as follows; the first layer
704
a
is about 5 to 15 nm, the second layer
704
b
is about 5 to 15 nm, and the third layer film
704
c
is about 5 to 15 nm. Reference numeral
709
denotes an insulator film.
To write information in this nonvolatile memory cell, a predetermined voltage is applied to the diffusion layer (source region)
707
B and the gate electrode
703
of the select MOS transistor to turn on the select MOS transistor and a predetermined voltage is applied to the diffusion layer (drain region)
707
A and the gate electrode
705
of the memory MOS transistor respectively. At this time, for example, 0 V is applied to the source region
707
B, 1 to 2 V is applied to the gate electrode of the select MOS transistor, 3 to 5 V is applied to the drain region
707
A, and 8 to 10 V is applied to the gate electrode
703
of the memory MOS transistor to inject electrons into the silicon nitride film
704
b
that is part of the gate capacitor insulator.
To erase information from the nonvolatile memory cell, a negative bias is applied to the memory gate electrode
705
and a positive bias to the diffusion layer
707
A of the memory MOS transistor respectively to inject hot hales into the charge trapping film

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