Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-24
2004-08-24
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S365000, C365S185220, C365S185280, C438S258000, C438S263000
Reexamination Certificate
active
06781188
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device. More particularly, the invention relates to a nonvolatile semiconductor memory device having a floating gate element.
2. Description of the Background Art
For example, Japanese Patent Laying-Open No. 11-17035 discloses a conventional nonvolatile semiconductor memory device.
FIG. 28
is a plan view of the conventional nonvolatile semiconductor memory device disclosed in the publication.
FIG. 29
is a cross section taken along line XXIX—XXIX of FIG.
28
.
FIG. 30
is a cross section taken along line XXX—XXX of FIG.
28
.
FIG. 31
is a cross section taken along line XXXI—XXXI of FIG.
28
.
Referring to
FIG. 28
, a memory region
500
and a peripheral region
600
are formed on a silicon substrate
401
. In the memory region
500
, bit lines
420
extend so as to perpendicularly cross control gate electrodes
410
. In peripheral region
600
, a plurality of gate electrodes
434
are formed, and an isolation oxide film
430
is positioned between gate electrodes
434
. Memory region
500
in which a memory transistor is formed and peripheral region
600
in which a transistor having gate electrode
434
is formed are electrically isolated from each other by an LOCOS (Local Oxidation of Silicon) film
449
.
Referring to
FIGS. 29 and 30
, memory region
500
is shown by cross sections of regions
200
and
300
. A memory transistor has n-type impurity regions
413
a
and
413
b
as drain regions, an n-type impurity region
414
as a source region, a silicon oxide film
404
, a floating gate electrode
407
, an ONO (Oxide Nitride Oxide) film
408
, a silicon oxide film
409
, and control gate electrode
410
.
Impurity regions
413
a
and
413
b
and impurity region
414
are formed in the surface of p-type silicon substrate
401
with a predetermined distance from each other. Floating gate electrode
407
is formed on regions sandwiched by impurity regions
413
a
and
413
b
and impurity region
414
via silicon oxide film
404
.
Control gate electrode
410
is formed so as to extend over floating gate electrode
407
via ONO film
408
consisting of three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and silicon oxide film
409
.
On silicon substrate
401
, a bottom n-well
402
and a p-well
403
in contact with bottom n-well
402
are formed. A trench
405
is formed between floating gates
407
arranged in a predetermined direction, and a silicon oxide film
406
is formed so as to fill trench
405
.
The upper end face of silicon oxide film
406
is positioned between the top face and bottom face of floating gate electrode
407
. On silicon oxide film
406
and floating gate electrode
407
, ONO film
408
, silicon oxide film
409
, control gate electrode
410
, and a TEOS (Tetra Ethyl Ortho Silicate) oxide film
411
are formed.
A p-type pocket region
415
is formed so as to surround impurity region
414
. On side walls of floating gate electrode
407
, ONO film
408
, silicon oxide film
409
, control gate electrode
410
, and TEOS oxide film
411
, a side wall oxide film
412
is formed.
An interlayer insulating film
416
is formed over silicon substrate
401
so as to cover the memory transistor. In a part of interlayer insulating film
416
, contact holes
417
reaching impurity regions
413
a
and
413
b
are formed. A doped polysilicon layer
420
a
is formed so as to fill the contact holes
417
and cover interlayer insulating film
416
.
Bit line
420
constructed by doped polysilicon layer
420
a
which is in contact with interlayer insulating film
416
and a tungsten silicide layer
420
b
is formed. An interlayer insulating film
421
is formed so as to cover interlayer insulating film
416
and bit line
420
. A silicon oxide film
422
is formed on interlayer insulating film
421
, and an aluminum interconnection
423
is formed so as to be buried in silicon oxide film
422
. A smooth coat film
424
is formed so as to be in contact with silicon oxide film
422
and aluminum interconnection
423
and, further, an aluminum interconnection
425
is formed on smooth coat film
424
.
Referring to
FIG. 31
, peripheral region
600
is expressed by a region
800
shown in FIG.
31
. Isolation oxide film
430
is formed in silicon substrate
401
. A p-well
431
and an n-well
432
are formed by using isolation oxide film
430
as a border.
On p-well
431
, a transistor having gate electrode
434
, a silicon oxide film
433
, and an n-type low-density impurity region
437
and an n-type high-density impurity region
438
serving as source/drain regions is formed. On n-well
432
, a transistor having gate electrode
434
, silicon oxide film
433
, and a p-type low-density impurity region
439
and a p-type high-density impurity region
440
serving as source/drain regions is formed. A silicon oxide film
435
is formed on gate electrode
434
, and a side wall oxide film
436
is formed on the side walls of gate electrode
434
and silicon oxide film
435
.
Interlayer insulating films
416
and
421
are formed so as to cover the transistors. Contact holes
441
reaching silicon substrate
401
are formed in interlayer insulating films
416
and
421
. A plug
442
is formed so as to fill contact hole
441
. Aluminum interconnection
423
is formed so as to be buried in silicon oxide film
422
and to be in contact with interlayer insulating film
421
and plug
442
. Smooth coat film
424
is formed on silicon oxide film
442
, and an aluminum interconnection
443
is formed so as to be buried in smooth coat film
424
. Aluminum interconnection
425
which is in contact with aluminum interconnection
443
is formed on smooth coat film
424
.
FIGS. 32 and 33
are cross sections showing fabricating processes of the nonvolatile semiconductor memory device illustrated in FIG.
30
. Referring to
FIG. 32
, on silicon substrate
401
, bottom n-well
402
, p-well
403
, a silicon oxide film
463
, doped polysilicon
464
, and an ONO film
466
are sequentially formed. A silicon oxide film, doped polysilicon, a tungsten silicide layer, and a TEOS oxide film are formed so as to cover ONO film
466
. A resist is applied so as to cover the TEOS oxide film and patterned in a predetermined shape, thereby forming a resist pattern
469
. By etching the TEOS oxide film, tungsten silicide layer, doped polysilicon, and silicon oxide film by using resist pattern
469
as a mask, TEOS oxide film
411
, control gate electrode
410
, and silicon oxide film
409
are formed. After that, resist pattern
469
is removed.
Referring to
FIG. 33
, the whole silicon substrate
401
is covered with a resist, and the resist is patterned in a predetermined shape, thereby forming a resist pattern
470
. By etching ONO film
466
, doped polysilicon
464
, and silicon oxide film
463
along resist pattern
470
, ONO film
408
, floating gate electrode
407
, and silicon oxide film
404
are formed. After that, resist pattern
470
is removed.
Impurity regions
413
a
and
413
b
, pocket region
415
, side wall oxide film
412
, interlayer insulating film
416
, bit line
420
, interlayer insulating film
421
, aluminum interconnection
423
, silicon oxide film
422
, smooth coat film
424
, and aluminum interconnection
425
are sequentially formed, thereby completing the nonvolatile semiconductor memory device shown in FIG.
30
.
In the method of fabricating the nonvolatile semiconductor memory device as described above, as shown in
FIG. 33
, the memory gate in which floating gate electrode
407
and control gate electrode
410
are overlapped with each other has a vertically-long shape. In an etching process, etching of floating gate electrode
407
positioned in the lowest layer needs high-precision dimensional control. Since the memory gate itself has the vertically-long shape, there is a problem such that the dimensional control is difficult. It is also difficult to prevent accumulation of an etching residue between neighboring f
McDermott Will & Emery LLP
Nelms David
Nguyen Dao H.
Renesas Technology Corp.
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