Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2003-03-04
2004-03-16
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185110
Reexamination Certificate
active
06707742
ABSTRACT:
Japanese Patent Application No. 2002-74598, filed on Mar. 18, 2002, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device having a reference cell array in addition to a regular cell array, respectively arranged with memory cells.
There is known as an example of a nonvolatile semiconductor memory device of the Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate (MONOS) type having, between the channel and the gate, a gate insulation film formed by the layers of a silicon oxide film, a silicon nitride film and a silicon oxide film, in order to trap charges in the silicon nitride film.
The MONOS-type nonvolatile semiconductor memory device is disclosed in a publication, Y. Hayashi, et al.: 2000 Symposium on VLSI Technology, Digest of Technical Papers, p. 122 to p. 123. This document discloses a MONOS flash memory having one word gate and two nonvolatile memory cells (also called MONOS memory cells) of under control of two control gates. Namely, one flash memory cell has two electron trap sites.
By arranging a plurality of such structured MONOS flash memory cells in row and column directions, a regular cell array is configured.
The operation of such a flash memory includes data erasure, programming and reading out. Data programming and reading out is simultaneously effected usually on 8 bits, 16 bits or 32 bits while data erasure is simultaneously on multiple bits.
During data reading, the cell currents, for example, from sixteen selected cells are inputted to sixteen sense amplifiers and compared with a reference current, thereby determining a memory state of each selected cell.
It can be considered that a constant reference voltage is set up in order to supply such a reference current. However, the location of sixteen selected cells changes every time depending upon address selection. Moreover, there is change in cell current characteristic depending upon a cell location due to the cause of manufacture. The cell current characteristic refers to temperature characteristic, voltage characteristic and so on. Accordingly, there possibly arises a case that the memory state of a selected cell cannot be correctly determined upon supplying a reference current to the sense amplifier on the basis of such constant reference voltage.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a nonvolatile semiconductor memory device having a reference cell array in addition to the regular cell array thereby reducing the characteristic variation between the cell currents to be simultaneously selected and read out by the both arrays and compared by a sense amplifier.
A nonvolatile semiconductor memory device according to the present invention has a regular cell array and a reference cell array. The regular cell array may be configured by arranging a plurality of memory cells in row and column directions, each of the memory cells having one word gate and first and second nonvolatile memory cells controlled by first and second control gates, respectively. The reference cell array may be configured by arranging a plurality of reference memory cells in the row and column directions, each of the reference memory cells having the same structure as each of the memory cells.
The regular cell array has M numbers of large blocks formed by dividing the regular cell array in the column direction, and each of the M numbers of large blocks has m numbers of small blocks formed by finely dividing each of the large blocks in the column direction. Each of the m numbers of small blocks becomes a minimum unit of manufacture process of cell array.
The number and arrangement of the reference memory cells within the reference cell array are coincident with number and arrangement of the memory cells arranged in each of the m numbers of small blocks as a minimum array unit within the regular memory cell.
This can approximate the positional dependence of the cells within the reference cell array to the positional dependence of the cells within the small block as a minimum array unit in the regular cell array.
The small block can be defined as follows. Each of the m numbers of small blocks may have a plurality of sub-bit lines extending along the column direction, and each of the sub-bit lines may be commonly connected to the first and second nonvolatile memory cells that are adjacent each other in two of the memory cells adjacent in the row direction in each row. In this manner, the nonvolatile memory cells in the adjacent two columns within the small block may share one sub-bit line.
Another definition of the small block may be as follows. First, a plurality of main bit lines extending across the M numbers of large blocks along the column direction may be provided. M numbers of bit-line select switches may be arranged on each column, the bit line select switches selecting one of the m numbers of sub-bit lines positioned on the same column within each of the m numbers of small blocks and connecting the selected one of the sub-bit lines to one of the main bit lines. Regions of the two small blocks adjacent in the column direction may be demarcated by a formation region of each of the m numbers of bit-line select switches on each column.
A further definition of the small block may be as follows. Each of the m numbers of small blocks may have a plurality of sub-control gate lines extending along the column direction, and each of the sub-control gate lines may be commonly connected to the first and second control gates that are adjacent each other in two of the memory cells adjacent in the row direction in each row. In other words, the nonvolatile memory cells in the adjacent two columns within the small block may share one sub-control gate.
The designation for a selected cell in the regular cell array and reference cell array during data reading may be as follows. During the data reading, a low-level address from among row addresses and column addresses to be used for cell selection in the regular cell array, may be used to execute cell selection in the reference cell array. This is because the number and arrangement are equal between the cells arranged in one small block of the regular cell array and those in the reference cell array.
During data reading, one of the first and second nonvolatile memory cells in one of the memory cells may be designated as a selected cell and the other may be designated as an unselected opposite cell. At this time, a select voltage may be applied to one of the first and second control gates corresponding to the selected cell within the regular cell array and an override voltage may be applied to the other of the first and second control gates corresponding the unselected opposite cell. On the other hand, the select voltage may be applied to both of the selected cell and the unselected opposite cell of the reference memory cell within the reference cell array. This is because the reference memory cell has been set in an erased state upon factory shipment, and the reference memory cell does not require an override voltage for a control gate of a cell unknown in memory state.
The regular cell array may be divided in the row direction into n numbers of first memory blocks, one of the n numbers of first memory blocks being designated as a redundant memory block. Similarly, the reference cell array may be divided in the row direction into n numbers of second memory blocks, one of the n numbers of second memory blocks being a reference redundant memory block.
In this case, the nonvolatile semiconductor memory device may further include: n numbers of sense amplifiers provided correspondingly to the n numbers of first memory blocks; a first path circuit which supplies cell current from the selected cell in each of the n numbers of first memory blocks to each of the n numbers of sense amplifiers; and a second path circuit which supplies reference cell current from the selected cell in each of the n numbers of second memory blocks to each of the n numbers of sense amplifiers.
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Kamei Teruhiko
Kanai Masahiro
Le Vu A.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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