Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2001-09-27

2003-06-17

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S147000

Reexamination Certificate

active

06580633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to a semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device.
2. Background Art
Among various kinds of semiconductor memory devices, a FeRAM (a ferroelectric memory) has memory cells, in each of which a gate electrode
21
A and a source region
22
A of, for example, an N-channel type MIS transistor are electrically connected to a word line WL and a bit line BL, respectively, and a ferroelectric capacitor
30
A is electrically connected between a drain region
23
A and a plate line PL of this MIS transistor, as is seen from FIG.
10
(A) showing an equivalent circuit thereof.
In the case of such a kind of a semiconductor memory device
1
A, when one of binary data “1” and “0”, for instance, data “1” is written to a memory cell
10
A, the word line WL is set at a high level (H) in a state in which the bit line BL is maintained at the high level (H), while the plate line PL is maintained at a low level (L). Consequently, the MIS transistor
10
A is put into an on-state. Thus, in the ferroelectric capacitor
30
A, an electrode
31
A electrically connected to the drain region
23
A of the MIS transistor
10
A is set at the high level (H), while an electrode
32
A electrically connected to the plate line PL thereof is set at the low level (L), as illustrated in FIG.
10
(B). This results in occurrence of polarization in a ferroelectric layer of the ferroelectric capacitor
30
A.
In contrast with this, when data “0” is written to the memory cell
10
A (that is, when deleting data written thereto), the word line WL is set at the high level (H) in a state in which the bit line BL is maintained at the low level (L) and the plate line PL is set at the high level (H), as illustrated in FIG.
11
(A). Consequently, the MIS transistor
10
A is brought into an on-state. In the ferroelectric capacitor
30
A, an electrode
31
A electrically connected to the drain region
23
A of the MIS transistor
10
A is set at the low level (L), while an electrode
32
A electrically connected to the plate line PL is set at the high level (H), as illustrated in FIG.
11
(B). Thus, the ferroelectric layer of the ferroelectric capacitor
30
A is polarized in a direction opposite to the direction of polarization in the case of writing the data “1” thereto.
Next, an operation of reading information is described hereinbelow. First, the bit line BL is precharged at ground potential. Thereafter, the bit line BL is put in a high impedance state. Subsequently, the electric potential of the plate line PL is fixed at ground potential. At that time, the ferroelectric capacitor
30
A is maintained in the polarized state as before. Then, the plate line PL is set at the high level (H). At that time, charges are discharged from the ferroelectric capacitor
30
A. The amount of the discharged charge varies with a direction in which the polarization is previously caused. Moreover, the discharged electric charge appears as a voltage of the bit line BL. Thus, it is determined by amplifying this voltage by means of a sense amplifier which of“1” and “0” the data represents.
However, in the case of the conventional FeRAM, when information is read, the ferroelectric capacitor
30
A discharges. Thus, it is necessary for holding the data to write the data thereto again. That is, in the case of the conventional FeRAM, a destructive read operation is performed. Meanwhile, generally, in the case of FeRAMs, the number of times of writing data is limited. Therefore, in the case of the destructive read operation, the writing of data is needed every time information is read. Consequently, the scope of applications of the conventional FeRAM is extremely limited.
Thus, problems to be solved by the present invention reside in constituting a memory cell from one transistor and one capacitor and in providing a non-volatile semiconductor memory device that can read data nondestructively.
SUMMARY OF THE INVENTION
To solve the foregoing problems, according to a first aspect of the present invention, there is provided a semiconductor memory device, which first, comprises at least a plurality of memory cells each formed by stacking a plate electrode, a ferroelectric layer, an insulating film, a channel region of a MIS (Metal Insulator Semiconductor) transistor, a gate insulating film of the MIS, and a gate electrode of the MIS transistor in this order. A word line is electrically connected to the gate electrode of each of the plurality of memory cells. First and second bit lines are electrically connected to a source region and a drain region of the MIS transistor, respectively. A plate line is electrically connected to the plate electrode.
In the specification of the present application, the term “MIS” is strictly for the purpose of representing a structure and does not mean that the gate electrode is limited to a metallic one. The term “MIS” implies that, for example, a doped silicon film may be used as the gate electrode.
According to the first aspect of the present invention, the MIS transistor is, for instance, a thin film transistor.
In the semiconductor memory device of the present invention, when data is stored in the memory cell, a voltage of a polarity corresponding to the data is applied between the plate line and each of the first and second bit lines. Moreover, a gate voltage for turning on the MIS transistor is applied to the gate electrode from the word line.
For example, when one kind of binary data is stored in the memory cell, a voltage of a polarity corresponding to the one kind of binary data is applied between the plate line and each of the first and second bit lines. Moreover, a gate voltage for turning on the MIS transistor is applied to the gate electrode from the word line. In contrast, when the other kind of binary data is stored in the memory cell, a voltage of a polarity opposite to the polarity of the voltage applied in the case of storing the one kind of data is applied between the plate line and each of the first and second bit lines. Moreover, a gate voltage for turning on the MIS transistor is applied to the gate electrode from the word line.
When data is written thereto in this manner, electric charges corresponding to the polarity of the voltage applied between the plate line and each of the first and second bits are stored in the ferroelectric layer.
In the semiconductor memory device constructed in this way, the channel region of the MIS transistor is affected in a manner varying according to the polarity of the polarized ferroelectric layer by the charges stored in the ferroelectric layer. This results in change in the source-drain-current-gate-voltage characteristic of the MIS transistor. Thus, let “a first gate voltage” represent a gate voltage, at which the source-drain current reaches a predetermined level according to the source-drain-current-gate-voltage characteristic of the MIS transistor, when one kind of binary data “1” and “0” is written thereto. Further, let “a second gate voltage” represent a gate voltage, at which the source-drain current reaches a predetermined value, when the other kind of binary data “1” and “0” is written thereto. Moreover, let “a data reading gate voltage” represent an electric potential level between the first and second gate voltages. When a reading voltage is applied between the source and the drain of the MIS transistor while the data reading gate voltage is applied to the gate electrode from the word line, it is detected from the first bit line or the second bit line whether or not a source-drain current flows. Consequently, it is decided which kind of the data “1” and “0” is written thereto.
When data is read in this way, the charges stored in the ferroelectric layer merely electrostatically affect the channel region and are not discharged in the semiconductor memory device according to the present invention. Therefore, even when the data written to the memory cells are read, the electric charges having been stored in the ferroelectric layer remai

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