Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2001-05-03

2002-10-22

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S346000, C257S387000, C257S607000

Reexamination Certificate

active

06469348

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and the process for the same, in particular, to a nonvolatile semiconductor memory device and the process for the same that has been improved so as to increase performance and reliability.
2. Description of the Background Art
In recent years, a flash memory, which is a type of nonvolatile semiconductor memory device, has been expected to become widely used as a next generation memory device since it can be manufactured at a lower cost than dynamic random access memories (DRAM).
FIG. 11
is a cross section view of a memory cell part of a conventional flash memory. As shown in
FIG. 11
, a source
2
, connected to a source line, and a drain
3
, connected to the corresponding bit line, are provided on the surface of the semiconductor substrate
1
.
A floating gate electrode
5
for storing information is provided above the semiconductor substrate
1
with a tunnel oxide film
4
interpolated in between. A control gate electrode
7
connected to the corresponding word line is provided above the floating gate electrode
5
with an interlayer insulating film (for example, a layered film of oxide film
itride film/oxide film (ONO film))
6
interpolated in between.
Erasing or writing is carried out by injecting electrons into the floating gate electrode
5
or by extracting electrons stored in the floating gate electrode
5
through the FN (Fowler-Nordheim) current phenomenon, the channel hot electron (CHE) phenomenon, or the like, in the tunnel oxide film
4
located directly beneath the floating gate electrode
5
. Due to the condition of the electrons in the floating gate electrode
5
, a binary condition of the threshold value is created so that “0” or “1” is read out based on the condition.
Among floating gate type nonvolatile semiconductor memories such as the above flash memories, or EEPROMs, the array configuration which is used most generally is the NOR type array. The NOR type array has contacts formed above the drain diffusion layers of the memory cell transistors of each row and has bit lines formed of metal wires, polycide wires, or the like, in the row direction. That is to say, the NOR type array is in the array configuration where the gate wires of the memory cell transistors of each column and the bit lines are formed in a matrix condition.
FIG. 12
is a circuit diagram showing the NOR type array.
FIG. 13
is a diagram showing a layout of the NOR type array.
FIG. 14
is a cross section view along the line
300
—
300
in FIG.
13
.
FIG. 15
is cross section view along the line
400
—
400
in FIG.
13
.
FIG. 16
is a cross section view along the line
500
—
500
in FIG.
13
. In these figures, bit line contacts are denoted as
8
, active regions are denoted as
9
, an isolation oxide film is denoted as
10
and an oxide film is denoted as
11
.
Referring to these figures, all of the sources
2
of the memory cell transistors of each block (for example, formed of memory cell transistors of 512 Kbits) are connected. At the time when all of the sources
2
are connected in this manner, it is very useful to use the self-aligning source structure for miniaturization of the memory cell transistors.
The self-aligning source structure is not formed in the manner wherein, at the time of connection of the sources
2
of respective memory cell transistors, a contact part is formed above the diffusion layer of each memory cell transistor so that these are connected through a metal wire.
In the self-aligning source technology, first a control gate electrode
7
of a memory cell transistor is formed as shown in
FIG. 17 and
, after that, a resist
12
is formed in order to make an opening for the source
2
only.
An end part of the resist
12
is formed above the control gate electrode
7
. As shown in
FIGS. 16 and 17
, an isolation oxide film existing above the source
2
is etched and removed by using the resist
12
and the control gate electrode
7
as mask materials.
In addition, As is introduced into the sources
2
through ion injection. Thereby, respective sources
2
are connected through the diffusion layer in the column direction. These are formed through self-alignment. Here, the part shown by a broken line in
FIG. 16
represents the isolation oxide film removed through etching.
In the case that all of the sources of the memory cell transistors are formed in the active region and they are connected through a metal wire, room for alignment becomes necessary so that the gate intervals of the sources must be made large.
In the self-aligning source technology, however, since the sources of memory cell transistors are connected through a diffusion layer, the gates sandwiching the sources of the memory cell transistors and the gate intervals can be formed according to the minimum design rule. As a result, the miniaturization of the memory cell transistors can be implemented.
Together with the remarkable scaling down of the design rule in recent years, however, the gate length, which can be formed according to the minimum design rule, has been becoming increasingly shorter in a flash memory to which the self-aligning source structure is applied.
In this case, the short channel effect of the memory cell transistors becomes large and, therefore, the cells do not operate properly according to punch through unless the channel concentration is enhanced or unless the pocket structure (for example, a structure providing a p
+
pocket region around an n type source) is adopted.
In the case of n type memory cell transistors, boron (B) is generally used for channel injection or for formation of pocket regions. It is widely known that, in the case that boron is injected excessively, however, a crystal defect
13
occurs in the substrate
1
, as shown in
FIG. 18
, due to the subsequent heat treatment.
As a result, a leak is caused between the source and the drain of the memory cell transistor so as to significantly lower the device performance. In addition, in the case that the crystal defect
13
extends below the tunnel oxide film
4
, the reliability, such as endurance, retention, or the like, is significantly lowered.
FIG. 19
shows a process flow in the first prior art from the formation of the first and second layered gates
20
a
,
20
b
, as shown in
FIG. 18
, to the formation of the sidewall spacers.
First, as shown in
FIG. 20
, the first and second layered gates
20
a
,
20
b
are formed. Next, as shown in
FIG. 21
, a resist
28
for opening the source part of the cell, only, is formed through a photomechanical process. By using the resist
28
as a mask, etching for removing the isolation oxide film and ion injection for converting the removed part into a diffusion layer wire are carried out so as to complete a self-aligned source.
As for the ion injection in this case, As injection for forming the source which is a diffusion layer wire is carried out. In the case of preventing punch through by means of a high concentration injection into the channel, a high concentration injection of boron into the cell part is carried out after the formation of the isolation oxide film and before the formation of the tunnel oxide film
4
.
In the case of the cell of the pocket structure, a high concentration injection of boron is carried out in addition to the As injection in the self-aligning source process.
Next, as shown in
FIG. 22
, the resist
28
is removed and, as shown in
FIG. 23
, an insulating film
14
is deposited for the formation of the sidewall spacers. After that, as shown in
FIG. 24
, sidewall oxidation of the floating gate electrode
5
and the control gate electrode
7
is carried out for the purpose of rounding the source edge and drain edge of the floating gate electrode
5
. Next, as shown in
FIG. 25
, the insulating film
14
is etched back and the sidewall spacers
18
are formed.
FIG. 26
is a process flow showing the process of the second prior art. As shown in
FIG. 27
, the first and second layered gates
20
a
,
20
b
a

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