Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-02-12
2002-06-18
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189050, C365S230080
Reexamination Certificate
active
06407954
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular to nonvolatile semiconductor memory device having an automatic multi-byte write function.
2. Description of the Related Art
In a nonvolatile semiconductor memory device shown in
FIG. 8
, memory cell region is divided into a plurality of sectors S
1
, S
2
, . . . , Sn−
1
and Sn, a Y selector
2
is provided for the memory cell array
1
of each of the sectors S
1
, S
2
, . . . , Sn−
1
and Sn, and a logic circuit
3
for selecting each Y selector
2
is incorporated.
A sense amplifier
4
and a write circuit
5
are connected in parallel to a bit line
1
a
of each memory cell array
1
, and data are input to and output from the sense amplifier
4
and the write circuit
5
that are connected in parallel via an I/O buffer
6
. Numerals
7
are a plurality of I/O terminals provided corresponding to the I/O buffers
6
.
In the nonvolatile semiconductor memory device according to related art shown in
FIG. 8
, in order to carry out multiple write into the plurality of sectors S
1
, S
2
, . . . , Sn−
1
and Sn, a plurality (4 bytes) of bit lines
1
a
are selected simultaneously by the logic circuit
3
based on a multi-program test mode entry signal
8
, and the same data are written simultaneously to the corresponding memory cell arrays from each write circuit
5
.
Now, when the multi-program is adopted in a nonvolatile semiconductor memory device as shown in
FIG. 8
, it is necessary after the completion of the operation to check the result of the write by a write verify test mode in order to confirm whether or not the data are written normally.
However, in the test mode it is necessary to apply a voltage of about 7V to the word lines of the memory cell arrays from an external power supply terminal that is not shown. It incurs an additional test time of 5 ns/address and results in a drawback of diluting the effect of reducing the test time.
In order to resolve the above problem possessed by the nonvolatile semiconductor memory device shown in
FIG. 8
, a method in which an automatic write operation is carried out, having a test after write as an on-chip incorporated function, has been proposed.
In
FIG. 9
is shown a nonvolatile semiconductor memory device having the function of an automatic write operation according to related art.
The nonvolatile semiconductor memory device according to related art shown in
FIG. 9
is formed by adding a data control circuit
9
and a status circuit
10
to the circuit shown in FIG.
8
.
The data control circuit
9
holds write data input from the I/O buffer
6
, and outputs write data to the write circuit
5
at the time of writing. At write inspection, the data control circuit
9
compares data read from the sense amplifier
4
with the write data stored in it, and outputs data (data about the result of the write check for the memory cell array
1
) about whether or not they match with each other (write pass) to the status circuit
10
.
The status circuit
10
, with the write inspection decision data as an input, outputs pass/fail decision data that indicate whether or not successful write to the memory cell array
1
was obtained, to the I/O terminal
7
and an operation control circuit
11
.
The operation control circuit
11
completes the write operation to the memory cell array
1
when the write inspection decision data for the memory cell array
1
is a pass, and controls so as to repeat a rewrite and an inspection on the rewrite to the memory cell array
1
when the decision data is a fail.
Next, the operation of the nonvolatile semiconductor memory device shown in
FIG. 9
will be described. When an operation command, and subsequent data to be written and an address signal are input from the outside to the memory device, the input data are held in the data control circuit
9
from the I/O terminal
7
via the buffer
6
.
When the write operation to the memory cell array
1
is started under the control of the operation control circuit
11
in this state, the write data held in the data control circuit
9
are written through the write circuit
5
to the memory cell in the sector S
1
, S
2
, . . . , Sn−
1
or Sn selected by the input address signal.
Next, when the write inspection operation to the memory cell array
1
is started under the control of the operation control circuit
11
, the data control circuit
9
reads the write inspection data for the memory cell array
1
through the sense amplifier
4
, compares the write inspection data with the write data that are stored in the data control circuit
9
, and outputs data (write inspection decision data for the memory cell array
1
) as to whether or not they match (write pass) to the status circuit
10
.
In the meantime, the status circuit
10
, with the write inspection decision data for the memory cell array
1
output from the data control circuit
9
as an input, takes the logical product of the pass/fail decision data which indicate whether or not all the memory cell arrays
1
were successfully written, and when the write to all the memory cell arrays
1
is normally completed, outputs a signal to that effect to the I/O terminal
7
.
When the write inspection decision data for the memory cell arrays
1
is a pass, the operation control circuit
11
completes the write operation to the memory cell array
1
, resets all the operations, and sets the relevant components to a standby state for the next operation.
When the write inspection decision data indicates a fail, the operation control circuit
11
controls the memory cell array
1
to be subjected to a rewrite of data and an inspection of the rewriting.
However, in the case of automatic write operation for the nonvolatile semiconductor memory device according to the related art shown in
FIG. 9
, the pass/fail decision data are output by being taken the logical product at a single I/O terminal
7
. Accordingly, when a defective product is to be saved by means of redundancy, it becomes necessary to verify again as to the write operation to which memory cell array
1
was decided to be in failure.
Moreover, for the verify mode, it is necessary to apply a voltage of about 7V to the word line of the memory cell array from the terminal of an external power supply, where the test time is Sns/address (write time) so that it results in a problem that a long time is wasted for the test.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a nonvolatile semiconductor memory device which is capable of suppressing the increase in write time due to the increase in the number of parallel write caused by the multiple write, and omitting analogous to the automatic write the time for write verify.
In order to achieve the above object, in a nonvolatile semiconductor memory device having memory cell region divided into a plurality of sectors, the nonvolatile semiconductor memory device according to the present invention makes it possible to write simultaneously write data to the memory cell arrays divided into the plurality of sectors, and output the inspection result of the write to the outside by scanning the address signals.
In a nonvolatile semiconductor memory device having memory cell arrays divided into a plurality of sectors, the nonvolatile semiconductor memory device according to this invention includes, write means for simultaneously writing write data to the memory cell arrays divided into the plurality of sectors, write inspection means for conducting write inspection as to match/mismatch between the data written to the memory cell array and the write data to be written to the memory cell array, and outputting pass/fail decision data indicating whether or not the memory cell array was successfully written, hold means for holding the pass/fail decision data for the memory cell array, and output means for outputting to the outside the pass/fail decision data arranged to correspond to each memory cell array in response to the externally input address
Ninomiya Kazuhisa
Sekiguchi Mitsuru
Hutchins, Wheeler & Dittmar
Le Vu A.
NEC Corporation
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