Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2001-08-08

2002-12-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S218000, C365S189020

Reexamination Certificate

active

06496427

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device that stores information in floating gates.
2. Description of the Related Art
A nonvolatile semiconductor memory stores information by the presence or absence of charge accumulated on floating gates. Examples of such a nonvolatile semiconductor memory include a flash memory, which erases information in memory cells simultaneously.
FIG. 24
shows the configuration of a conventional flash memory array. In
FIG. 24
, reference numeral
1
is a nonvolatile memory cell including a floating gate and a control gate,
2
is a word line connected to the control gate of the nonvolatile memory cell
1
,
3
is a bit line, and
4
is a source line. As shown in
FIG. 24
, each nonvolatile memory cell
1
is formed independently at the intersection of the word line
2
and the bit line
3
.
To erase data from the nonvolatile memory cells
1
, a high voltage is applied to the word lines
2
and the source lines
4
. At the time of erasing, the same voltage VNEG is applied to all the word lines via switching elements
5
selected by an erasing block decoder
6
. For reading and writing, each of the nonvolatile memory cells is selected independently by a selecting circuit (not shown in FIG.
24
). Like the word lines
2
, the same voltage VPOS is applied simultaneously to the source lines
4
during erasing. In other words, data is erased at once during erasing.
The nonvolatile memory includes a redundant memory cell array
8
, which is located adjacent to a normal memory cell array
7
, to repair memory defects in a redundant manner. The normal memory cell array
7
and the redundant memory cell array
8
share the bit lines
3
. When a redundant word line
2
R is used, the word line having a defective bit is not used.
However, an erasing voltage is applied to the cells connected to the defective word line because the erasing circuit is the same. Consequently, those cells are over-erased, compared with the cells connected to other normal word lines
2
. Thus, the memory cells connected to the defective word line are depleted to cause bit-line leakage during reading, resulting in malfunction.
To solve the problem, e.g., JP 7(1995)-230700 A discloses a method for preventing the application of an erasing bias to the source line of a replaced defective cell. Using this method, however, the erasing bias is applied to the word line. Therefore, charge is drawn from the floating gate, which may cause over-erasing.
There is another method in which a redundant word line is provided or each erasing block, as shown in FIG.
25
. For example, when a second formal erasing block
72
is found to be defective, it is replaced by a redundant erasing block
8
, as shown in FIG.
25
. Since the second normal erasing block
72
is not accessed permanently, no erasing bias is applied thereto. Therefore, such over-erasing as described above does not occur.
However, the erasing block is usually composed of tens to hundreds of kilobits as a unit, and the size of a unit to be replaced for one defective cell is the same as that of the erasing block. Thus, the repair efficiency is rather poor.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a nonvolatile semiconductor memory device that can prevent over-erasing even if a memory cell is replaced in the word line direction and provide high repair efficiency.
To achieve the above object, a first nonvolatile semiconductor memory device of the present invention includes: N (N is a natural number) normal memory cell arrays, a redundant memory cell array, (N+1) erasing bias circuits, N erasing decode circuits, and N redundancy control circuits. Each of the N normal memory cell arrays includes the arrangement of two or more nonvolatile memory cells, each having a control gate and a floating gate. The redundant memory cell array includes the arrangement of two or more nonvolatile memory cells, each having the same configuration as that of the nonvolatile memory cell in the normal memory cell array. The (N+1) erasing bias circuits apply an erasing bias for erasing data stored in the N normal memory cell. arrays and the redundant memory cell array. The N erasing decode circuits decode defective address information. The N redundancy control circuits are connected in series so that a preceding stage controls the next in order to store the defective address information for switching the (N+1) erasing bias circuits based on the defective address information responsive to output signals from the respective N erasing decode circuits. The (N+1) erasing bias circuits inhibit application of the erasing bias to word and source lines connected to the control gates of any one of the N normal memory cell arrays that is replaced by the redundant memory cell array and also inhibit application of the erasing bias to word and source lines connected to the control gates of the unused redundant memory cell array under a switching operation by the N redundancy control circuits in erasing data.
In the first nonvolatile semiconductor memory device, it is preferable that the size of an array of the N normal memory cell arrays is the same as that of the redundant memory cell array and is equal to or less than that of a minimum erasing block.
In the first nonvolatile semiconductor memory device, it is preferable that the (N+1) erasing bias circuits apply the erasing bias to any number of memory cell arrays among the N normal memory cell arrays and the redundant memory cell array under a switching operation by the N redundancy control circuits based on output signals from the N erasing decode circuits.
In the first nonvolatile semiconductor memory device, it is preferable that each of the N redundancy control circuits includes an input terminal, a first output terminal, and a second output terminal. The input terminal receives an output signal from the erasing decode circuit and a defective address program activation signal. The first output terminal switches an erasing bias activation signal and outputs it to one of the adjacent erasing bias circuits, and the second output terminal switches the erasing bias activation signal and outputs it to the other erasing bias circuit. It is also preferable that the second output terminal of one of the adjacent redundancy control circuits and the first output terminal of the other redundancy control circuit are connected in common. Each of the N redundancy control circuits stores the defective address information based on the output signal from the erasing decode circuit when the defective address program activation signal is activated, and among the N redundancy control circuits, a redundancy control circuit storing the defective address information controls the next redundancy control circuit so as to switch the terminals for outputting the erasing bias activation signal.
The above configuration can eliminate over-erased memory cells because no erasing bias is applied to the unused word and source lines of a memory cell array. Therefore, it can prevent malfunction due to bit-line leakage. Moreover, this configuration enables the replacement of a normal memory cell array by a redundant memory cell array for each word line, thus providing a higher repair efficiency than that of a conventional replacement for each erasing block.
In the first nonvolatile semiconductor memory device, it is preferable that each of the N redundancy control circuits includes a nonvolatile memory cell having a control gate and a floating gate to store the defective address information.
In such a case, it is preferable that each of the N redundancy control circuits includes the following: a nonvolatile memory cell having a gate connected to the preceding redundancy control circuit, a source connected to a first power line, and a drain connected to a common node; a first PMOS transistor having a gate connected to the gate of the nonvolatile memory cell, a source connected t

Affiliated with

Also associated with

Rating

Nonvolatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2918329