Nonvolatile semiconductor memory device

Static information storage and retrieval – Read/write circuit – Simultaneous operations

Reexamination Certificate

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Details

C365S148000, C365S189011, C365S218000

Reexamination Certificate

active

07957203

ABSTRACT:
A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

REFERENCES:
patent: 6618286 (2003-09-01), Kato et al.
patent: 6888773 (2005-05-01), Morimoto
patent: 7248494 (2007-07-01), Oh et al.
patent: 7535746 (2009-05-01), Kawazoe et al.
patent: 7649777 (2010-01-01), Ichige et al.

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