Nonvolatile semiconductor memory circuits

Details Nonvolatile semiconductor memory circuits Nonvolatile semiconductor memory circuits

1980-10-31

1982-07-27

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365189, G11C 1300

Patent

active

043421016

ABSTRACT:
An NMOS non-volatile latch having N-channel drivers Q.sub.1 and Q.sub.2 and variable threshold N-channel FATMOS transistors Q.sub.3 and Q.sub.4 as depletion loads. The control gate of each FATMOS transistor is coupled to its own node (X.sub.1 or X.sub.2) so as to operate in depletion, whereas to obtain the correct voltage stresses the tunnels of the FATMOS floating gates are cross-coupled to the opposite latch nodes.

REFERENCES:
patent: 4004284 (1977-01-01), Haren

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