Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-03-31
2000-09-05
Hardy, David
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257314, 36518518, H01L 29788
Patent
active
061147249
ABSTRACT:
An electrically erasable programmable read only memory (EEPROM) cell including a tunnel dielectric layer formed over a semiconductor substrate. The EEPROM cell may have a floating gate transistor and a select transistor. The floating gate transistor may have a floating gate formed over the tunnel dielectric and a control gate formed over the floating gate. The select transistor may have a first gate formed over the tunnel dielectric and a second gate formed over the first gate. The second gate may be electrically connected to the first gate.
REFERENCES:
patent: 5197027 (1993-03-01), Challa
patent: 5216268 (1993-06-01), Chen et al.
patent: 5222040 (1993-06-01), Challa
patent: 5297081 (1994-03-01), Challa
patent: 5323351 (1994-06-01), Challa
patent: 5326999 (1994-07-01), Kim et al.
patent: 5357465 (1994-10-01), Challa
patent: 5408431 (1995-04-01), Challa
patent: 5414658 (1995-05-01), Challa
patent: 5439838 (1995-08-01), Yang
patent: 5471422 (1995-11-01), Chang et al.
patent: 5508955 (1996-04-01), Zimmer et al.
patent: 5596529 (1997-01-01), Noda et al.
patent: 5698879 (1997-12-01), Aritome et al.
patent: 5706228 (1998-01-01), Chang et al.
patent: 5729493 (1998-03-01), Morton
patent: 5856691 (1999-01-01), Hazama
patent: 5914514 (1999-06-01), Dejenfelt et al.
M. Momodomi et al., "New Device Technologies for 5V-Only 4mb EEPROM with Nand Structure Cell", pp. 142-145, Reprinted from the IEDM Tech. Dig., pp. 142-145, 1988.
Barcella et al., "A 70ns CMOS Double Metal 16Mbit EPROM with Hierarchical Word Line Decoder", IEEE Nonvolatile Semiconductor Memory Workshop, pp. 3 pgs total (Aug. 14, 1995).
John Stuart Kleine, U.S. Patent application No. 08/537,131 entitled, "Structure and Process for a Gouge-Free Stacked Non-Volatile Memory Cell with Select Gate", pp. 50 pages total, filed on Sep. 29, 1995.
Onoda et al., "A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory", Apr. 1992, IEEE, pp. 24.3.1-24.3.4.
Cypress Semiconductor Corporation
Hardy David
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