Nonvolatile semiconductor memory apparatus

Details Nonvolatile semiconductor memory apparatus Nonvolatile semiconductor memory apparatus

2002-06-21

2004-06-08

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189040

Reexamination Certificate

active

06747902

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor nonvolatile memory device and an information processing system employing such a memory device, to an effective technique for, for example, a batch erasable type EEPROM (electrically erasable and programmable read only memory), and also to a microcomputer system employing such an EEPROM.
As a semiconductor nonvolatile memory device, there are known an erasable programmable read-only memory (referred to as an “EPROM”) the stored information on which is erasable by utilizing ultraviolet radiation, and also an electrically erasable and programmable read-only memory (referred to as an “EEPROM”) the stored information of which is electrically erasable. An EPROM is suitable for a large-scale memory capacity because areas of memory cells for storing information are relatively small. However, to erase the information stored in EPROM, it is necessary to irradiate ultraviolet rays to the memory cells. To this end, a package having an ultraviolet irradiating window, which is relatively expensive, would be required in order to be able to employ such type of memory cells. Moreover, in order to be able to write or rewrite new information by a programmer, the EPROM must be removed, during write/rewrite operations thereof, from the system to which this EPROM has been actually packaged in, thereby resulting in a problem.
On the other hand, with respect to an EEPROM, the information stored therein is electrically erasable and writable, while the EEPROM remains packaged in a system. However, areas associated with memory cells of the EEPROM type are relatively large. For instance, a typical area of a memory cell in an EEPROM is 1.5 to 2 times, or as much as approximately 2.5 to 5 times, larger than that of an EPROM. Such an EEPROM is described, for example, in “Electronic Technology—June 1988”, pages 122-127, issued by K.K. Nikkan Kogyo Shimbun, in which a detailed description is made of a construction of an EEPROM cell of a floating-gate tunnel oxide (FLOTOX), a mechanism of injection of electrons into a floating gate and of release of electrons from the floating gate, and the like.
The EEPROM cell of the FLOTOX type is a memory cell having a two-layer construction provided with a floating gate for holding electrons in the lower layer of a control gate. This mechanism is designed so that a tunnel current called a Fowlor-Nordheim (F-N) is allowed to flow through a region (a tunnel region) of an extremely thin insulating film formed in a portion of an insulating film between the floating gate and a drain region to effect injection of electrons into the floating gate and release of electrons from the floating gate.
In the memory cell of EEPROM of the FLOTOX type, electrons held by the floating gate are released, for example, by applying a GND voltage (0 V) to the control gate and applying a high voltage of 15 V to 20 V to the drain electrode.
As a result of this relatively large size of the memory cells, in general, EEPROM is not suitable when emphasis is in having a large memory capacity.
Semiconductor nonvolatile memory devices that can be considered as being between or intermediate the EPROM and EEPROM, are so-called “electrically batch erasable type EEPROM” devices, or are flash EEPROM devices, which have very recently been developed. These devices are the semiconductor nonvolatile memory devices in which either all of the memory cells formed in a chip, or a certain memory cell group among the memory cells formed in the chip, are electrically erased. In accordance with the electrically batch erasable type of EEPROM, or the flash EEPROM, the size of memory cells thereof can be formed to be substantially the same as that of EPROM.
Such an electrically batch erasable type EEPROM is described in, for instance, IEEE INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE in 1980, on pages 152 to 153; IEEE INTERNATIONAL SOLID-STATE CIRCUIT CONFERENCE in 1987, on pages 76 to 77; and IEEE, J. SOLID-STATE CIRCUITS, vol. 23 (1988), pages 1157 to 1163.
In
FIG. 16
, there is represented a schematic sectional view of the electrically batch erasable EEPROM, which has been disclosed in the International Electron Device Meeting held in 1987. The memory cell shown in
FIG. 16
is very similar to the memory cell of the normal EPROM. That is to say, this memory cell is constructed in accordance with an insulated gate type field-effect transistor (simply referred to as a “MOSFET” or “transistor”), however, having a double layer gate structure. In the structure of
FIG. 16
, reference numeral
8
indicates a P type silicon substrate; reference numeral
11
denotes a P type diffusion layer formed on the silicon substrate
8
; reference numeral
10
represents an N type diffusion layer having a low concentration formed on the silicon substrate
8
; and reference numeral
9
indicates an N type diffusion layer formed on each of the P type diffusion layer
11
and N type diffusion layer
10
. Also, reference numeral
4
represents a floating gate formed on the P type silicon substrate
8
via a thin oxide film
7
. Reference numeral
6
denotes a control gate formed on this floating gate
4
via the oxide film; reference numeral
3
indicates a drain electrode; and reference numeral
5
represents a source electrode. In other words, the memory cell shown in
FIG. 16
is constructed like a MOSFET but having instead the N-channel type double gate structure. Thus, the information is stored in this transistor, and is held in this transistor in accordance with effecting a change of the threshold voltage thereof.
It should be noted that a transistor (referred to as a “storage transistor”) of a memory cell, for storing information, discussed herein is of an N-channel storage transistor unless stated otherwise in the following description.
The information writing operation with respect to the memory cell represented in
FIG. 16
is similar to that of EPROM. In other words, the writing operation of EEPROM shown in
FIG. 16
is performed by injecting into the floating gate
4
a hot carrier produced adjacent to the drain region
9
connected to the drain electrode
3
. The threshold voltage of the storage transistor with respect to the control gate
6
is higher than that of another storage transistor which does not perform the writing operation, while such a writing operation is carried out. In the erasing operation, on the other hand, the control gate
6
is grounded, and the high voltage is applied to the source electrode
5
, whereby the high electric field is produced between the floating gate
4
and the source region
9
connected to the source electrode
5
. Then, while utilizing the tunneling phenomenon via the thin oxide film
7
, the electron which has been stored in the floating gate
4
is drawn via the source region
9
to the source electrode. As a result, the stored information disappears. In other words, the threshold voltage of the storage transistor is lowered with respect to the control gate
6
. During the reading operation, in order to prevent a weak writing operation from being undesirably effected to the above-described memory cell, that is, to prevent undesired carriers from being injected into the floating gate, the voltages applied to both the drain electrode
3
and control gate
6
are limited to a relatively lower value. A lower voltage of, for instance, on the order of 5 volts is applied to the control gate
6
. A magnitude of a channel current flowing through the storage transistor is detected in accordance with such applied voltages so as to determine whether or not the information stored in the memory cell corresponds to “0” or “1.”
In general, during the electrical erasing operation, when the erasing operation is continued for a long time, the threshold voltage of the storage transistor will become different from that of the storage transistor under the thermal balance, namely it may become a negative value. To the contrary, in case of EPROM where the stored information is erased by way of ultraviolet radiation, the threshold vo

Affiliated with

Also associated with

Rating

Nonvolatile semiconductor memory apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3310221