Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-03-23
2003-06-10
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185010, C365S185110, C257S317000, C257S318000
Reexamination Certificate
active
06577533
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2000-89100, filed on Mar. 28, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and a method of manufacturing the same, and particularly relates to a nonvolatile semiconductor memory having a NAND-type memory cell unit structured by connecting a plurality of memory cell transistors in series and a method of manufacturing the same.
2. Related Background Art
An EEPROM which enables electrical rewrite has been hitherto known as one of semiconductor memories. Especially, a NAND-type EEPROM in which a NAND-type memory cell unit is structured by connecting a plurality of memory cell transistors in series has attracted considerable attention as one capable of high integration.
FIG. 41
is a diagram showing an equivalent circuit of the NAND-type memory cell unit, and
FIG. 42
is a diagram showing the structure of a memory cell portion of the NAND-type memory cell unit in plan view. This example in
FIG. 42
shows the NAND-type memory cell unit in the case where STI (Shallow Trench Isolation) is used for isolating elements.
One memory cell transistor MT of the NAND-type EEPROM has an FETMOS structure in which a floating gate FG (a charge storage layer) and a control gate CG are stacked with an insulating film therebetween above a semiconductor substrate, a plurality of memory cell transistors are connected in series with their respective adjoining ones sharing a source/drain to constitute the NAND-type memory cell unit. The NAND-type memory cell units like this are arranged in a matrix form to constitute a memory cell array.
A drain D at one end side of the NAND-type memory cell unit is connected to a bit line BL via a select gate transistor ST
31
, while a source at the other end side of the NAND-type memory cell unit is connected to a common source line SL via a select gate transistor ST
32
. The control gate CG of the memory cell transistor MT and gate electrodes of the select gate transistors ST
31
and ST
32
are respectively connected to compose a word line WL and a select gate line in a direction perpendicular to the direction of the bit line BL.
As shown in
FIG. 42
, in the NAND-type EEPROM, one source/drain line formed out of a diffusion layer in a silicon active region is formed for one bit line BL. Namely, one NAND-type memory cell unit is formed for one bit line BL. Assuming that a design rule is F (Feature size), the line/space of the bit line BL is 1 F/1 F, and the line/space of the word line WL is also 1 F/1 F. Therefore, the cell size of one memory cell transistor MT is 2 F×2 F=4 F
2
. Since the select gate transistors ST
31
and ST
32
are provided in one NAND-type memory cell unit, the substantial one cell size is 4 F
2
+&agr; if the sizes of these select gate transistors ST
31
and ST
32
are taken into account as an overhead &agr;.
As a widely known example of such a NAND-type EEPROM, there are reports such as “A 3.3 V 32 MB NAND Flash Memory with Incremental Step Pulse Programming Scheme” by K. -D. Suh et al. in IEEE J. Solid-State Circuits, vol. 30, pp. 1149-1156, November 1995 and “A 35 ns Cycle Time 3.3 V Only 32 MB NAND Flash EEPROM” by Y. Iwata et. al. in IEEE J. Solid-State Circuits, vol. 30, pp. 1157-1164, 1995. In these references, the operation of a related NAND-type EEPROM is explained.
FIG. 43
is a diagram showing an equivalent circuit of a nonvolatile semiconductor memory having AND-type memory cell units, and
FIG. 44
is a diagram showing the structure of a memory cell portion of the AND memory cell unit in plan view.
The name of an AND type originates in that its connection mode is the same parallel connection as an NOR type and that its logic mode is inverse to the NOR type. Namely, as shown in
FIG. 43
, the AND-type memory cell unit has a sub-bit line SBBL and a sub-source line SBSL, and a plurality of memory cell transistors MT are connected in parallel between the sub-bit line SBBL and the sub-source line SBSL. For example, in the case of a 64 Mbits AND-type nonvolatile semiconductor memory, 128 memory cell transistors are connected in parallel in one AND-type memory cell unit.
The sub-bit line SBBL is connected to a main bit line MBL via a select gate transistor ST
41
. The sub-source line SBSL is connected to a main source line MSL via a select gate transistor ST
42
.
A memory cell array composed of these AND-type memory cell units is characterized by its pseudo contactless structure, in which the main bit line MBL and word lines WL are made hierarchical and the sub-bit line SBBL and the sub-source line SBSL are formed out of a diffusion layer. Writing/erase into/from the memory cell transistor MT is performed by an FN (Fowler-Nordheim) tunnel current. Specifically, the writing to the memory cell transistor MT is performed by extracting electrons in the floating gate FG to the drain side by the use of the FN tunnel current. The erase from the memory cell transistor MT is performed by injecting electrons from the semiconductor substrate to the floating gate FG by the FN tunnel current on the entire surface of a channel.
As shown in
FIG. 44
, in the AND-type memory cell unit, two lines in total, i.e. the sub-source line SBSL and the sub-bit line SBBL formed of the diffusion layer in the silicon active region, are formed for one main bit line MBL. Hence, the line/space of each of the sub-source line SBSL and the sub-bit line SBBL is 1 F/1 F, and the line/space of the word line WL is also 1 F/1 F. Consequently, the cell size of one memory cell transistor MT is 2 F×4 F=8 F
2
. Moreover, since the select gate transistors ST
41
and ST
42
are provided in one AND memory cell unit, the substantial one cell size is 8 F
2
+&agr; if the sizes of these select gate transistors ST
41
and ST
42
are taken into account as an overhead &agr;.
Meanwhile, Japanese Patent Laid-open No. Hei 7-45797 discloses a nonvolatile semiconductor memory in which a vertical NAND memory cell unit is formed in a side wall portion of a trench in order to reduce one cell size.
FIG. 45
is a diagram showing a cross section of a memory cell transistor MT portion of the nonvolatile semiconductor memory disclosed in this Japanese Patent Laid-open No. Hei 7-45797.
As shown in
FIG. 45
, in this nonvolatile semiconductor memory, a trench region TC is formed on a semiconductor substrate, and memory cell transistors MT are formed respectively on both side wall portions of this trench region TC. In this case, the floating gates FG are formed along a side wall on the inside of the trench region TC, and source/drains SD are formed as a diffusion layer along a side wall of the trench region TC of the semiconductor substrate. Namely, in this NAND-type memory cell unit, a plurality of memory cell transistors MT are each formed along the side wall of the trench region TC, and thus a source/drain current flows along the side wall of the trench region TC. The bit line BL is formed via an interlayer dielectric for each NAND-type memory cell unit. The line/space of this bit line BL is 1 F/1 F.
In order to attain higher integration, however, it is necessary to lay two source-drain lines formed in silicon active regions within a 2 F bit line pitch and to effectively reduce the memory cell size by half.
SUMMARY OF THE INVENTION
The present invention is made in view of the aforesaid problems. An object of the present invention is to three-dimensionally make an NAND-type EEPROM and lay two source/drain lines in silicon active regions within 2 F bit line pitch, that is, to provide two NAND-type memory cell units for one bit line, and thereby to provide a nonvolatile semiconductor memory capable of reducing the memory cell size by half, resulting in a reduction in bit cost and to provide a method of manufacturing the same.
In order to accomplish the aforementioned and other objects, a
Sakui Koji
Watanabe Toshiharu
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