Nonvolatile semiconductor memory and manufacturing method...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S314000, C257S315000, C257S316000, C257S320000, C257SE21209, C257SE21210, C257SE21179, C257SE21182, C257SE29300, C257SE29309, C257SE21324, C438S257000

Reexamination Certificate

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07825458

ABSTRACT:
A nonvolatile semiconductor memory includes a source area and a drain area provided on a semiconductor substrate with a gap which serves as a channel area, a first insulating layer, a charge accumulating layer, a second insulating layer (block layer) and a control electrode, formed successively on the channel area, and the second insulating layer is formed by adding an appropriate amount of high valence substance into base material composed of substance having a sufficiently higher dielectric constant than the first insulating layer so as to accumulate a large amount of negative charges in the block layer by localized state capable of trapping electrons, so that the high dielectric constant of the block layer and the high electronic barrier are achieved at the same time.

REFERENCES:
patent: 2006/0163676 (2006-07-01), Shimizu et al.
patent: 2006/0170033 (2006-08-01), Lee et al.
patent: 2006/0211205 (2006-09-01), Jeon et al.
patent: 2008/0217680 (2008-09-01), Shimizu et al.
patent: 2006-270102 (2006-10-01), None
patent: 10-0674965 (2007-01-01), None
U.S. Appl. No. 12/405,626, filed Mar. 17, 2009, Shingu, et al.
U.S. Appl. No. 12/051,274, filed Mar. 19, 2008, Shimizu, et al.
U.S. Appl. No. 12/189,400, filed Aug. 11, 2008, Shimizu, et al.
U.S. Appl. No. 12/714,841, filed Mar. 1, 2010, Shimizu, et al.

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