Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-05-30
2003-03-11
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S185050, C365S185290
Reexamination Certificate
active
06532165
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to nonvolatile semiconductor memory using ferroelectrics, and its driving method.
2. Description of the Related Art
A ferroelectric memory is a kind of nonvolatile memory enabling quick rewriting by using quick polarization inversion of a ferroelectric thin film and its residual polarization. There are some types of ferroelectric memory, i.e. a type using a ferroelectric capacitor (FeRAM type) and a type connecting ferroelectrics to a gate portion of a transistor (ferroelectric gate type). The ferroelectric gate type is superior in terms of its cell area and non-destructive read-out mode. As this ferroelectric gate type nonvolatile memory, there are known MFS (Metal-Ferroelectrics-Semiconductor) type memory and, MFIS (Metal-Ferroelectrics-Insulator-Semiconductor) type memory and MFMIS (Metal-Ferroelectrics-Metal-Insulator-Semiconductor) type memory.
Although the ferroelectric gate type nonvolatile memory is advantageous in being excellent in terms of its cell area and non-destructive read-out mode, since a one-transistor type operates in a simple matrix driving mode upon polarization inversion of the ferroelectrics, it involves the problem of “disturbance” which is a phenomenon that polarization of the ferroelectrics of selected memory cells exerts its influence also to the ferroelectrics of non-selected memory cells. That is,
FIG. 1
shows a part of a memory cell array of one-transistor type ferroelectric gate type nonvolatile memory. MC
11
′, MC
12
′, MC
21
′ and MC
22
′ are memory cells made of ferroelectric gate type transistors. B
1
a′, B
1
b′, B
2
a′ and B
2
b′ are bit lines. W
1
′ and W
2
′ are word lines. In this example, it operates in a simple matrix write mode, a disturb voltage of −Vw/3 (where Vw is a voltage necessary for polarization inversion of the ferroelectrics) is applied to the gate every time when data is written in other memory cells. In this case, data can be written with a lower voltage in a shorter time than with a flash memory configured to inject electric charges into floating gates. However, this is a reason of its weakness against the disturbance. Further, for The purpose of suppressing the disturb voltage to −Vw/3, it is necessary to render transistors of non-selected memory cells conductive as well to make a channel. Therefore, the extent of changes of the threshold voltage by the ferroelectrics is greatly limited, and the extent of characteristics the ferroelectrics are required to have is narrow. Furthermore, since it needs wiring connection to the source region and the drain region for each transistor of a a memory cell, the cell area increases as compared with a NAND type memory, and microminiaturized processing of the ferroelectrics is required. Therefore, its ferroelectric property deteriorates, and this makes it difficult to use ferroelectric materials, such as SBT, which are difficult to process by dry etching such as reactive ion etching (RIE).
The problem of the disturbance mentioned above can be overcome by adding selection transistors to memory cells. In this case, however, the cell area increases, and difficulty of high integration arises as a new problem.
On the other hand, flash memory is known as a kind of nonvolatile memory. Flash memory is configured to store information by injection and drawing of electrons to and from floating gates. Flash memory needs a larger voltage and a longer time for injection of electrons than polarization inversion of ferroelectrics, but this alleviates the disturbance problem. As a kind of flash memory, there has been developed NAND type memory having a small cell area and arranging a plurality of transistors in series to enable high integration.
Since ferroelectric gate type nonvolatile memory has a basic structure similar to that of flash memory, it is expected that the cell area decreases when the NAND type is employed. However, because of the above-indicated problem of disturbance and difficulty of ON/OFF control of transistors without polarization inversion, and because the directions of gate voltage application and changes of the threshold voltage are opposite from those of flash memory, NAND type cell arrangement has been difficult heretofore in ferroelectric gate type nonvolatile memory.
Japanese Patent Laid-Open Publication No. Hei 5-136377 and Japanese Patent Laid-Open Publication No. Hei 5-136378 propose NAND type nonvolatile memory devices. However, these NAND type nonvolatile semiconductor memory devices have extremely complicated structures which are considered difficult to realize.
OBJECTS AND SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide nonvolatile semiconductor memory enabling realization of NAND type nonvolatile semiconductor memory of high integration, quick operation, low power consumption and less disturbance, and a driving method thereof.
According to the first aspect of the invention, there is provided nonvolatile semiconductor memory characterized in that each memory cell is made of a dual gate transistor in which a ferroelectric is connected to one of gate portions thereof, a plurality of the memory cells are connected in series to form a memory block, and a plurality of the memory blocks are arranged to form a memory cell array.
In the first aspect of the invention, the memory block is typically made by connecting a plurality of memory cells in series and connecting a selection transistor at least at one end of the serial connection of the memory cells. The number of memory cells forming the memory block is basically arbitrary, and as the number of memory cells increases, they will be highly integrated. In this case, however, the path for the current flowing through transistors of the memory cells becomes longer, and this invites a voltage drop. Therefore, an optimum number of memory cells is selected depending upon the use of the nonvolatile semiconductor memory. One end of the memory block is connected to bit lines typically through the selection transistor. A dual gate transistor forming a memory cell is typically a thin-film transistor. More specifically, the dual gate transistor is a thin film transistor having, for example, a first gate electrode formed on one surface of a semiconductor via a first gate insulating film and a ferroelectric thin film, and a second gate electrode formed on the opposite surface of the semiconductor thin film via a second gate insulating film so as to oppose to the first gate electrode. In this case, the dual gate transistor forming the memory cell is switched by changing the voltage of the second gate electrode. The ferroelectric thin film extends continuously over the area of a plurality of memory cells, typically over the entire area of the memory cell array.
According to the second aspect of the invention, there is provided a method for driving a nonvolatile semiconductor memory in which each memory cell is made of a dual gate transistor in which ferroelectric is connected to one of a plurality of gate portions thereof, a plurality of the memory cells are connected in series to form a memory block, a plurality of the memory blocks are arranged to form a memory cell array, and each dual gate transistor is a thin film transistor having a first gate electrode formed on one surface of a semiconductor thin film via a first gate insulating film and a ferroelectric thin film, and a second gate electrode formed on the other surface of the semiconductor thin film via a second gate insulating film in a location opposed to the first gate electrode, comprising:
for an erasing operation, making uniform the direction of polarization of the ferroelectric thin film;
for a writing operation, making conduction of the dual gate transistors forming a plurality of the serially connected memory cells of the memory block selected through a selection transistor connected to a bit line by the second gate electrode, and inverting polarization of a part of the ferroelectric connect
Kananen, Esq. Ronald P.
Le Vu A.
Nguyen Hien
Sony Corporation
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