Static information storage and retrieval – Read/write circuit – Erase
Reexamination Certificate
2001-08-17
2002-10-01
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Erase
C365S185290, C365S189040, C365S230060
Reexamination Certificate
active
06459640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory using a nonvolatile transistor, and an automatic erasing/writing method thereof.
2. Description of the Prior Art
FIG. 26
is a block diagram showing the entire configuration of a conventional nonvolatile semiconductor memory. In the drawing, a reference numeral
1001
designates a nonvolatile semiconductor memory;
1002
designates a memory/memory decoder;
1003
designates a charge pump; and
1004
designates a dedicated control circuit including an MCU or the like.
The memory/memory decoder
1002
is composed of a memory block and a memory decoder. The memory block includes a plurality of small memory blocks having various integration degrees, a sense amplifier/writing circuit, a selector circuit, and so on. The memory decoder includes a row address latch, a column address input buffer latch, a row/column address pre-decoder, and so on (not shown). In addition, the charge pump
1003
includes a negative/positive voltage charge pump, and a reading pump (not shown). For details and operations, refer to the later description of the preferred embodiment.
Thus, the conventional nonvolatile semiconductor memory
1001
can execute memory controls such as automatic erasing/automatic writing/data reading and the like, by using the dedicated control circuit
1004
provided in the nonvolatile semiconductor memory
1001
. The dedicated control circuit
1004
provided in the nonvolatile semiconductor memory
1001
is a circuit specialized for executing only the memory control and, for an LSI or the like having a data processor and a nonvolatile semiconductor memory in the same chip, the scale of this dedicated control circuit
1004
has been enlarged to a level, which cannot be ignored.
International Publication WO99/01824 describes a method for controlling each control signal needed to control an EEPROM not by a dedicated control circuit but by a register block composed of a flip-flop in a semiconductor device with the built-in EEPROM. In recent years, however, in the case of a nonvolatile semiconductor memory incorporated in a microcontroller, there have been many kinds of signals to be controlled because of the presence of a charge pump for generating a voltage necessary for erasure/write inside the chip, and so on, and there have been a plurality of operation modes other than the erasure/write. Thus, by the register block composed of the flip-flop described in WO99/01824, it is impossible to perform an control by setting a plurality of control signals simultaneously active, or setting active control signals having a different combination every operation mode by the same timing.
In addition, for the conventional nonvolatile semiconductor memory, a memory array in the memory block composed of the memory array having a plurality of memory cells arranged in a matrix form can be replaced by a dummy memory array. This replacing processing can be carried out by separating or disconnecting a FUSE circuit provided in the nonvolatile semiconductor memory by laser.
Since the conventional nonvolatile semiconductor memory and the automatic erasing/writing method thereof have been constructed in the foregoing manner, there has been an inherent problem, i.e., the presence of the dedicated control circuit in the memory has brought about the increase of the circuit size of the LSI having the data processor and the nonvolatile semiconductor memory in the same chip.
Another inherent problem has been the impossibility of a direct verification whether the successful disconnection of the FUSE circuit is performed or not in the conventional nonvolatile semiconductor memory after it has been disconnected by laser.
Furthermore, in the conventional nonvolatile semiconductor memory, in order to replace the memory array in the memory block, composed of the memory array having the plurality of memory cells arranged in a matrix form, with the dummy memory cell array, there is no way other than a trimming processing for the FUSE circuit by laser. Alternatively, there are no methods of performing that replacement by using a pseudo replacement processing.
SUMMARY OF THE INVENTION
The present invention was made to solve the foregoing problems. Objects of the invention are to provide a nonvolatile semiconductor memory capable of eliminating a dedicated control circuit provided in the nonvolatile semiconductor memory by executing the automatic erasing/writing/data reading, and so on, of the nonvolatile semiconductor memory using a data processor provided in the same chip as that for the nonvolatile semiconductor memory, and thereby reducing the circuit size of the entire chip, and an automatic erasing/writing method thereof.
The other object is to provide a nonvolatile semiconductor memory capable of replacing a memory array in a memory block composed of the memory array having a plurality of memory cells arranged in a matrix form by a dummy memory, by providing a dummy register in the nonvolatile semiconductor memory, and setting a register value.
In accordance with a first aspect of the invention, there is provided a nonvolatile semiconductor memory, comprising: a memory bock composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; means for updating a content of the register by a data processor coupled to the register; and means for controlling the memory decoder and the charge pump by updating the content of the register.
In this case, the nonvolatile semiconductor memory may further comprise means for erasing data of the memory block by updating the content of the register.
The nonvolatile semiconductor memory may further comprise means for writing data in the nonvolatile transistor in the memory block by updating the content of the register.
Moreover, the nonvolatile semiconductor memory may further comprise means for reading data from the nonvolatile transistor in the memory block by updating the content of the register.
In accordance with a second aspect of the invention, there is provided an automatic erasing method of a nonvolatile semiconductor memory. The nonvolatile semiconductor memory includes: a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and the charge pump allocated to register 1 bit; and means for updating a content of the register by a data processor coupled to the register. The automatic erasing method comprises the step of: erasing data of the memory block by using the updating means to update the content of the register.
In accordance with a third aspect of the invention, there is provided an automatic writing method of a nonvolatile semiconductor memory. The nonvolatile semiconductor memory includes: a memory block composed of a memory array having a plurality of memory cells arranged in a matrix form, each of the memory cells being composed of a nonvolatile transistor; a memory decoder necessary for erasing/writing/reading data of the nonvolatile transistor in the memory array; a charge pump necessary for erasing/writing/reading the data of the nonvolatile transistor in the memory array; a register having each of a plurality of control signals for controlling the memory decoder and th
Hongo Katsunobu
Iba Tomohisa
Kamiya Mikio
Kimura Hiroyuki
Sezaki Toshihiro
Burns Doane , Swecker, Mathis LLP
Le Thong
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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