Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2007-06-22
2009-11-24
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030, C365S185180
Reexamination Certificate
active
07623384
ABSTRACT:
According to one embodiment, a nonvolatile semiconductor memory comprising: a source line side selection gate transistor that is having a first source region connected to a source line and a first gate electrode connected to a first select gate line; a bit line side selection gate transistor that is having a second drain region connected to a bit line and a second gate electrode connected to a second select gate line; a first memory cell string that is having a plurality of memory cell transistors connected in series, connected between a first drain region of the source line side selection gate transistor and a second source region of the bit line side selection gate transistor; and a second memory cell string that is having a plurality of memory cell transistors connected in series, connected in parallel with the first memory cell string; wherein the first memory cell string and the second memory cell string are stacked on a semiconductor substrate via an interlayer insulating film, wherein the source line side selection gate transistor and the bit line side selection gate transistor are placed on the semiconductor substrate.
REFERENCES:
patent: 6566698 (2003-05-01), Nishihara et al.
patent: 7272040 (2007-09-01), Mikolajick et al.
patent: 2004/0124466 (2004-07-01), Walker et al.
patent: 2004/0155302 (2004-08-01), Zhang
patent: 2007/0176218 (2007-08-01), Kang
patent: 2002-94020 (2002-03-01), None
patent: 2002-197857 (2002-07-01), None
Andrew J. Walker, et al., “3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications,” Symposium on VLSI Technology Digest of Technical Papers, 2003, 2 pages.
Mark Johnson, et al., “512-Mb PROM With a Three-Dimensional Array of Diode/ Antifuse Memory Cells,” IEEE Journal of Solid-State Circuits, vol. 38, No. 11, Nov. 2003, pp. 1920-1928.
Kang-Deong Suh, et al., “A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” IEEE, International Solid-State Circuits Conference, ISSCC, Session 7, Flash Memory, Paper TA 7.5, Digest of Technical Papers, Feb. 16, 1995, pp. 128-129 and p. 350.
Hoang Huan
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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