Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

2007-02-05

2008-12-09

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185050

Reexamination Certificate

active

07463540

ABSTRACT:
A memory cell array has a unit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data.

REFERENCES:
patent: 4636984 (1987-01-01), Neukomm
patent: 4996669 (1991-02-01), Endoh et al.
patent: 5043942 (1991-08-01), Iwata et al.
patent: 5379254 (1995-01-01), Chang
patent: 5412603 (1995-05-01), Schreck et al.
patent: 5515327 (1996-05-01), Matsukawa et al.
patent: 5523980 (1996-06-01), Sakui et al.
patent: 5541879 (1996-07-01), Suh et al.
patent: 5557124 (1996-09-01), Roy et al.
patent: 5559735 (1996-09-01), Ono et al.
patent: 5568420 (1996-10-01), Lim et al.
patent: 5592001 (1997-01-01), Asano
patent: 5592415 (1997-01-01), Kato et al.
patent: 5606527 (1997-02-01), Kwack et al.
patent: 5615152 (1997-03-01), Bergamont
patent: 5615163 (1997-03-01), Sakui et al.
patent: 5680346 (1997-10-01), Pathak et al.
patent: 5732018 (1998-03-01), Choi et al.
patent: 5740107 (1998-04-01), Lee
patent: 5754469 (1998-05-01), Hung et al.
patent: 5777925 (1998-07-01), Tokushige
patent: 5805498 (1998-09-01), Lee et al.
patent: 5841721 (1998-11-01), Kwon et al.
patent: 5963476 (1999-10-01), Hung et al.
patent: 5966601 (1999-10-01), Ling et al.
patent: 6014328 (2000-01-01), Onakado et al.
patent: 6044017 (2000-03-01), Lee et al.
patent: 6055188 (2000-04-01), Takeuchi et al.
patent: 6061270 (2000-05-01), Choi
patent: 6172905 (2001-01-01), White et al.
patent: 6175522 (2001-01-01), Fang
patent: 6535426 (2003-03-01), Michael et al.
patent: 7035143 (2006-04-01), Lee
patent: 7177190 (2007-02-01), Lee
patent: 7227782 (2007-06-01), Lee et al.
patent: 2006/0239069 (2006-10-01), Kamigaichi et al.
patent: 2006/0274579 (2006-12-01), Ha et al.
patent: 0440265 (1991-08-01), None
patent: 0704852 (1996-04-01), None
patent: 0797212 (1997-09-01), None
patent: 1-098194 (1989-04-01), None
patent: 2-232898 (1990-09-01), None
patent: 4-103095 (1992-04-01), None
patent: 7-230695 (1995-08-01), None
patent: 10-500801 (1998-01-01), None
patent: 10-079197 (1998-03-01), None
patent: 10-177797 (1998-06-01), None
patent: 10-188580 (1998-07-01), None
patent: 10-209406 (1998-08-01), None
patent: 11-195718 (1999-07-01), None
patent: 96-029704 (1996-09-01), None
“Session XII: ROMs, PROMs and EROMs THPM 12.6:A 16Kb Electrically Erasable Nonvolatile Memory”, William S. Johnson, et al. ISSCC 80/1980, IEEE International Solid-State Circuits Conference, CH 1490-2/80/0000/0152, pp. 152-153, Feb. 14, 1980.
“A New Flash E2Prom Cell Using Triple Polysilicon Technology”, Fujio Masuoka, et al., 464-467—IEDM 84, CH2099-0/84/0000-0464; 17.3 (1984).
“New Ultra High Density EDPROM And Flash EEPROM With NAND Structure Cell”, Fujio Masuoka, et al., CH2515-5/87/0000-0552 1987 IEEE, IEDM 87 pp. 552-555, May 1987.
Chapter 1 Basics of Nonvolatile Semiconductor Memory Devices, p. 70; Chapter 4 Floating Gate Flash Memories, p. 212; Chapter 5 SONOS Nonvolatile Semiconductor Memories, p. 316; p. 326, 5.1 The SONOS Nonvolatile Memory Transistor, p. 327: Chapter 5 SONOS Nonvolatile Semiconductor Memories, p. 344, undated.
European Search Report dated Sep. 22, 2000.
Art Lancaster et al., ISSCC Dig. Tech. Papers, “Nonvolatile Memory,” Feb. 1983, pp. 164-165.
Yoshiaki Kamigaki et al., IEEE J. of Solid-State Circuits, vol. 24, No. 6, “Yield and Reliability of MNOS EEPROM Products,” Dec. 1989, pp. 1714-1722.
Atsushi Nozoe et al., ISSCC99/Session 6/Paper MP6.5, “A 256 Mb Multilevel Flash Memory with 2MB/s Program Rate for Mass Storage Applications,” pp. 1-6.
Takeuchi, Ken, et al., “A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories,” IEICE Trans. Electron., vol. E79-C, No. 7, Jul. 1, 1996, pp. 1013-1020.
Choi, J.D., et al., “A New Double Boosting Program Scheme in Booster Plate NAND Flash Memories with 9V Programming,” Non-Volatile Semiconductor Memory Workshop, Aug. 1998, pp. 109-111.
EP Search Report dated Dec. 17, 2003, EP appln. No. 99117469.9.
JP Office Action mailed Mar. 14, 2006, JP appln. No. 11-010676.

Affiliated with

Also associated with

Rating

Nonvolatile semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Nonvolatile semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4050633