Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

1999-05-27

2001-02-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S233100, C365S230030

Reexamination Certificate

active

06191974

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a stably operable nonvolatile semiconductor memory and a high-speed accessible nonvolatile semiconductor memory.
BACKGROUND OF THE INVENTION
FIG. 20
is a schematic diagram illustrating a conventional flash EEPROM (Electrically Erasable Programmable Read-only Memory) which is a nonvolatile semiconductor.
With reference to
FIG. 20
, 1011~10
mn
denote MOS type memory cells each having a floating gate, and these memory cells are arranged in matrix. Sources of these memory cells are connected to Vs while drains thereof are connected to sources of N channel transistors
111
~
11
n
which are column gates. Control gates of the memory cells and gates of the N channel transistors (column gates) are connected to an address decoding means
2
. Further, drains of the column gates are connected to a current detection means
3
. Hereinafter, a memory composed of the above-described components is called a memory core unit
4
. Further, a timing generation means
50
is connected to the memory core unit
4
. The timing generation means
50
receives a clock and generates timing signals used for access to the memory core unit
4
. The timing signals generated in the timing generation means
50
are input to the address decoding means
2
and the current detection means
3
. Further, addresses are input to the address decoding means
2
.
In the flash EEPROM so constructed, readout of data is performed as follows. When an address is input to the address decoding means
2
, the addresss decoding means
2
selects a memory cell according to the address, and the current detection means
3
detects a current which flows in the selected memory cell and outputs the result of the detection. A description is now given of timing signals which are output from the timing generation means
50
during the data readout operation, with reference to FIG.
22
. Generally, a flash EEPROM is controlled by four internal signals, NCE (chip enable signal), SAE (sense amplifier enable signal), PRC (precharge signal), and DLE (data latch signal). Further, “clock” is a signal indicating an operating point, and “Dout” is data output from the output port. All the internal signals are generated according to rising of the clock. Read access is made in a LOW period of the NCE, and it is reset in a HIGH period of the NCE. In a HIGH period of the PRC, an event of precharging a word line and a bit line is performed. In this period, a word line and a bit line are selected by the address decoding means
2
and the current detection means
3
. In a period when the SAE is HIGH and the PRC is LOW, the sense amplifier (the current detection means
3
) performs an event of detecting a current flowing in the selected memory cell. In a LOW period of the DLE, an event of outputting the output data from the current detection means
3
directly to the output port is performed. In a HIGH period of the DLE, an event of latching the output data to hold it until the DLE becomes LOW is performed. By the internal operation comprising the plural events mentioned above, the data Dout (i.e., the result of readout) is sequentially output from the output port.
In recent years, high-speed semiconductor integrated circuits and systems using these ICs have been developed. Amongst these ICs and systems, especially microcomputers have made rapid progress in performance, and this progress has created a demand for higher-speed access of main storage memories which are generally low in access speed, such as mask ROMs and flash memory EEPROMs. In order to meet this demand, an interleaving method is adopted, in which a main storage memory is divided into a plurality of bank memories, and addressing is performed between the respective bank memories in the horizontal direction, whereby the speed of access to consecutive addresses is apparently increased.
FIG. 21
is a block diagram illustrating a conventional nonvolatile semiconductor memory performing interleaving, in which a main storage memory is divided into two bank memories. With reference to
FIG. 21
, two independently operable memory core units, i.e., a first bank memory
41
and a second bank memory
42
, are arranged in parallel. The first bank memory
41
is a storage area for even addresses, and the second bank memory
42
is a storage area for odd addresses. Further, a timing generation means
50
generates timing signals for access to each bank memory, in accordance with a clock and a bank address for selecting a bank memory. Each bank memory receives the addresses and the timing signals.
When the clock and the address are input to the nonvolatile semiconductor memory so constructed, the memory operates as shown in a timing chart of FIG.
23
. In
FIG. 23
, “first bank memory access” and “second bank memory access” indicate which addresses are accessed by the respective bank memories. Further, “first bank memory output” and “second bank memory output” indicate the outputs from the respective bank memories. Hereinafter, the operation of the nonvolatile semiconductor memory will be described with reference to
FIGS. 21 and 23
. Since interleaving is performed, consecutive addresses are sequentially input. Further, since access is started in synchronization with rising of the clock and the first and second bank memories operate alternately, data is output in each cycle of the clock. Actually, each bank memory makes access in two clock cycles. That is, by avoiding contention of access to the same bank memory, in response to a request for access to the consecutive addresses, data is output in a cycle half as long as the operation cycle (two clock cycles) of each bank memory. That is, as shown in
FIG. 23
, the first and second bank memories operate alternately, and data is output in each clock cycle.
In the conventional nonvolatile semiconductor memory, as shown by dotted-line arrows in
FIG. 22
, the internal timing signals are generated in synchronization with rising of the clock. Assuming that the clock cycle is 100 ns and the LOW period of the NCE is 80 ns, rising of the NCE is generated according to a signal which is 80 ns delayed from the rising of the clock. However, if a delay circuit is constituted by an RC or the like, the delay period varies due to variations of elements. When the delay period is reduced, the internal operation is not performed in time because of reduction in the sense period or the like, and the memory does not operate normally. On the other hand, when the delay period is increased, part of the delay period is included in the next access cycle and, also in this case, the memory does not operate normally. In either case, the operation period is not stable, whereby the memory does not operate normally.
Further, the conventional nonvolatile semiconductor memory employs the above-described interleaving method for high-speed operation. So, as shown in
FIG. 23
, when performing access to consecutive addresses, data is output in each clock cycle in the whole memory. However, if the access to consecutive addresses is interrupted due to a jump or the like during the interleaving operation, an access penalty occurs. To be specific, when a jump to address A
11
occurs according to the result of output data D
0
from address A
0
(i.e., when a jump from the first bank memory
41
to the second bank memory
42
occurs), a penalty equivalent to two clock cycles occurs from when data D
0
of address A
0
(origin address) is output until data D
11
of address A
11
(destination address) is output. When a jump from address A
12
to address A
20
occurs (i.e., when a jump occurs in the same bank memory), a penalty equivalent to three clock cycles occurs from when data D
12
of address A
12
is output until data D
20
of address A
20
is output, because the first bank memory
41
and the second bank memory
42
operate alternately. That is, when a jump occurs in a microcomputer, the access penalty varies according to the origin address and the destination address. Moreover, when the jump occurs in the same bank memory, a penalty as

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