Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

2000-03-16

2001-05-22

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Erase

C365S185220, C365S189070, C365S189090, C365S185330

Reexamination Certificate

active

06236609

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-074039, filed Mar. 18, 1999; and No. 11-074045, filed Mar. 18, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory particularly used as a NOR-type flash EEPROM.
A NOR-type flash EEPROM has three basic modes, i.e., a program mode, an erase mode and a read mode. In the program mode, for example, operation for raising the threshold voltage of a memory cell up to not less than a predetermined value (e.g., 5.5V) is carried out. In the erase mode, operation for setting the threshold voltage of a memory cell to fall within a predetermined range (e.g., 0.5 to 3.0V) is carried out.
In case of a NOR-type flash EEPROM having an auto-program function and an auto-erase function, in the program mode, for example, it is verified whether or not the threshold voltage of a memory cell is not less than 5.5V and reprogram (rewrite) is automatically carried out until the threshold voltage of the memory cell becomes not less than 5.5V. In the erase mode, it is verified whether or not the threshold voltage of a memory cell is within a range of 0.5 to 3.0V and predetermined operation is carried out automatically until the threshold voltage of the memory cell falls within the predetermined range.
FIG. 1
shows the important parts of a conventional NOR-type flash EEPROM.
A memory cell array
11
consists of a plurality of blocks. Each block has a plurality of memory cells connected between word lines (input side) and bit lines (output side) to form a NOR relationship.
External addresses A
1
to A
17
are input to a multiplexer
13
either directly or through an address register
12
. An address counter
16
generates internal addresses. The multiplexer
13
feeds either an external address or an internal address to a row decoder
14
and a column decoder
15
.
Input data is fed to a data input register
18
and a command register
19
through an input/output buffer
17
. The data of the data input register
18
is supplied to memory cells through a column selecting circuit
20
.
The command register
19
recognizes a command consisting of an address and a data and outputs a control signal to the address register
12
, the multiplexer
13
, the data input register
18
and a control circuit
21
in response to the command.
The control circuit
21
recognizes an operation mode to be executed next based on the control signal output from the command register
19
.
A potential generating circuit
22
generates various potentials corresponding to operation modes. The potential generated by the potential generating circuit
22
is applied to the control gates and the bit lines of the memory cells in each operation mode.
A verify circuit
23
verifies whether or not data program or data erase is surely carried out to a selected memory cell and outputs a result, i.e., VERIOK to the control circuit
21
.
A final address detecting circuit
24
outputs a detection signal AEND indicating whether or not the final address of each block of the memory cell array
11
is detected and outputs a detection signal BEND indicating whether or not the final block of the memory cell array
11
is detected.
A timer
25
counts the number of program operations or the number of erase operations conducted to the selected memory cell. The timer
25
outputs a time out signal TIME OUT to the control circuit
21
when the number of program operations or that of erase operations conducted to the selected memory cell reaches a predetermined number.
A clock generating signal
26
generates a clock for controlling the internal operation of the flash EEPROM based on a write enable signal {overscore (WE)}, a chip enable signal {overscore (CE)}, an output enable signal {overscore (OE)} and the like.
FIG. 2
shows the memory cell array of the NOR-type flash EEPROM shown in FIG.
1
.
FIGS. 3
to
5
show the device structure of a portion enclosed by a broken line X in FIG.
2
.
In this example, memory cells are formed in a twin well, i.e., a P-type twin well
112
in an N-type well
111
in a P-type silicon substrate
110
.
As an element separation insulating film, a field oxide film
113
, for example, is formed above the silicon substrate
110
. A silicon oxide film
114
, which serves as a gate insulating film, is formed on an element region surrounded by the field oxide film
113
. A floating gate electrode
115
is formed on the silicon substrate
114
. A control gate electrode (word line)
117
(WL) is formed above the floating gate electrode
115
through a silicon oxide film
116
.
An N-type source region
121
and an N-type drain region
122
are formed in the silicon substrate
110
on both sides of the floating gate electrode
115
and the control gate electrode
117
. In this case, the source regions (source lines SL's) of all memory cells, for example, are mutually connected.
A silicon oxide film
118
entirely covering memory cells MC's are formed on the memory cells MC's. A contact hole
120
which reaches a drain region
122
is provided in the silicon oxide film
118
. A bit line
119
(BL) is formed on the silicon oxide film
118
. The bit line
119
contacts with the drain region
122
through the contact hole
120
of the silicon oxide film
118
.
Next, description will be given to potentials applied to memory cells in each of the program mode, the read mode and the erase mode of the above-stated NOR-type flash EEPROM.
First, in the program mode, the potential of a selected word line WL is set at, for example, Vpp (e.g., a high potential such as about 10V) and that of an unselected word line WL is set at Vss (e.g., 0V). The potential of a bit line BL to which a memory cell (selected cell), for which “0”-programming is conducted, is connected is set at Vss (e.g., 0V). The potential of a bit lines BL to which a memory cell (unselected cell), for which “1”-programming is conducted, is connected is set at Vss (e.g., 0V). The potential of a source line SL is Vss (e.g., 0V).
At this moment, in the selected cell, the potential of a control gate (word line) is Vpp, that of a drain is Vdp and that of a source is Vss, so that electrons within the source are accelerated and moved to the drain. They become electrons (hot electrons) with high energy in a channel in the vicinity of the drain and are moved into the floating gate by an electric field between the control gate and the channel. Due to this, the threshold voltage of the selected cell increases and “0”-programming is carried out in the cell.
In the unselected cell, on the other hand, the potential of a control gate (word line) is Vpp and those of a drain and a source are Vss, so that no current flows between the drain and the source. Due to this, the threshold voltage of the unselected cell does not increase and “1”-programming is carried out (an erase state is maintained) in the cell.
Next, in the read mode, the potential of the selected word line WL is set at, for example, Vcc (e.g., a potential of about 5V) and that of the unselected word line WL is set at, for example, Vss (e.g., 0V). The bit line BL to which the memory cell (selected cell), for which data read is carried out, is pre-charged with Vd (e.g. a potential of about 1V) and then turned into a floating state. The potential of the bit line BL to which the memory cell (unselected cell), for which no data read is carried out, is set at, for example, Vss (e.g., 0V). The potential of the source line SL is set at, for example, Vss (e.g., 0V).
The threshold voltage of the memory cell (in a “1” state) storing data “1” is lower than Vcc, whereas that of the memory cell (in a “0” state) storing data “0” is higher than Vcc. Due to this, if the potential of the selected word line WL is set at Vcc, the cell in the “1” state is turned on and that in the “0” state is turned off.
Accordingly, a current flows into the cell in the “1” state and th

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