Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

1993-12-22

1995-12-05

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular connection

36518901, 36518905, 36523006, G11C 700, G11C 1140

Patent

active

054735637

ABSTRACT:
A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory block is erased by an erase voltage applied to a semiconductor substrate while unselected memory blocks are prevented from erasing by capacitive coupling of the erase voltage to floated word lines connected to control gates of memory transistors of the unselected memory blocks. In a program mode where a program voltage is applied to a selected word line of a selected memory block and a pass voltage is applied to unselected word lines of the selected memory block, channel regions and source and drain junctions of memory transistors of cell units in the selected memory block are charged to a program inhibition voltage. Channel regions and source and drain junctions of cell units associated with memory transistors programmed to the other binary data are discharged to be programmed while those of cell units associated with nonprogrammed memory transistors are maintained to the program inhibition voltage to prevent programming.

REFERENCES:
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5313432 (1994-05-01), Lin et al.
patent: 5345418 (1994-09-01), Challa
"New Device Technologies For 5V-Only 4Mb EEPROM With NAND Structure Cell" by M. Momodomi, R. Kirisawa, R. Nakayama, S. Aritome, T. Endoh, Y. Itoh, Y. Iwata, H. Oodaira, T. Tanaka, M. Chiba, R. Shirota, and F. Masuoka. ULSI Research Center, Toshiba Corporation. 42-IEDM 88.
"A Nand Structured Cell With A New Programming Technology For Highly Reliable 5V-Only Flash EEPROM", R. Kirisawa, S. Aritome, R. Nakayama, T. Endoh, R. Shirota, and F. Masuoka, 1990 Symposium on VLSI Technology.
"A High-Density NAND EEPROM With Block-Page Programming For Microcomputer Applications", Y. Iwata, M. Momodomi, T. Tanaka, H. Oodaira, Y. Itoh, R. Nakayama, R. Kirisawa, S. Aritome, T. Endoh, R. Shirota, K. Ohuchi, and F. Masuoka 1990 IEEE.
A 4-Mb NAND EEPROM with Tight Programmed Vt Distribution, M. Momodomu, T. Tanaka, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R. Shirota, K. Ohuchi and F. Masuoka 1990 IEEE.

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