Nonvolatile semiconductor device capable of increased...

Details Nonvolatile semiconductor device capable of increased... Nonvolatile semiconductor device capable of increased...

2000-06-06

2002-04-30

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000

Reexamination Certificate

active

06380585

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for fabricating the same, and a semiconductor integrated circuit.
2. Description of the Related Art
In various kinds of memory devices for portable units and various kinds of memory-incorporated logic VLSI's, the technologies for nonvolatile memory devices have recently become increasingly important because it is an urgent task to reduce the costs per bit, while further enhancing the electrical write functions thereof. In order to develop such a high-performance device with a reduced cost, various structures and fabrication processes have been suggested.
Hereinafter, examples of conventional nonvolatile semiconductor memory devices will be described.
FIG. 21
shows the cross section of a nonvolatile semiconductor memory device having a so-called “stack-type” structure. Such a structure was suggested by S. Mukherjee, et al. in IEEE IEDEM 1985, Technical Digest, p. 616.
In the device shown in
FIG. 21
, a tunnel oxide film
102
, a floating gate
103
, a capacitive insulating film
104
and a control gate
105
are stacked in this order on a semiconductor substrate
101
. In the surface of the semiconductor substrate
101
, a source region
106
and a drain region
107
, which have been doped with an impurity having a high concentration, are formed. The region between the source region
106
and the drain region
107
functions as a channel region. The floating gate
103
is formed so as to overlap the channel region. This nonvolatile semiconductor memory device has a “stacked gate structure” in which the control gate
105
is disposed over the floating gate
103
which is covered with oxide films in the periphery thereof. The floating gate
103
functions as a node in which information is stored and the stored information is variable between “0” and “1” depending upon the charged states thereof. The threshold voltage of a transistor as viewed from the control gate
105
is varied in accordance with the amount of charge accumulated in the floating gate
103
. By utilizing this phenomenon, the read of data is performed. On the other hand, the write of data is performed by utilizing the phenomenon that channel hot electrons, which have obtained high energy as a result of the acceleration caused by a high electric field in a lateral direction within an inversion layer of the channel, are injected into the tunnel oxide film
102
so as to reach the floating gate
103
. As will be described later, the efficiency with which the electrons, which have obtained high energy as a result of the acceleration caused by a high electric field in a lateral direction within an inversion layer of the channel, are injected into the tunnel oxide film
102
is extremely low. Thus, the write efficiency is also low. A high channel doping concentration is required to improve the write efficiency, resulting in the high threshold voltage and read current. The erasure of data is performed by taking out the electrons in the floating gate
103
into the source region
106
in accordance with a Fowler-Nordheim (FN) tunneling phenomenon. In order to utilize the FN tunneling phenomenon, a high electric field of about 10.5 V/cm to about 11 V/cm is required to be formed in the tunnel oxide film
102
. Thus, when data is erased, the control gate
105
is grounded (0 V) and a high voltage of about 15 V is applied to the source region
106
, for example.
FIG. 22
shows the cross section of a nonvolatile semiconductor memory device which has been suggested in order to suppress the decrease in cell operation margin when data is erased. Such a device is disclosed by H. Kume, et al. in IEEE IEDEM 1987, Technical Digest, p. 560.
In the device shown in
FIG. 22
, a tunnel oxide film
202
, a floating gate
203
, a capacitive insulating film
204
and a control gate
205
are stacked in this order on a semiconductor substrate
201
. In the surface of the semiconductor substrate
201
, a high-concentration source region
206
and a high-concentration drain region
207
, which have been doped with an impurity having a high concentration, are formed. In addition, an n
−
type low-concentration impurity layer
208
and a p
+
-type high-concentration impurity layer
209
are formed so as to cover the n
+
type high-concentration source region
206
and the n
+
-type high-concentration drain region
207
, respectively. The region between the n
−
type low-concentration impurity layer
208
and the n
+
-type high-concentration drain region
207
functions as a channel region. The floating gate
203
is formed so as to overlap the channel region and the ends of the floating gate
203
overlap a part of the high-concentration source region
206
and a part of the high-concentration drain region
207
, respectively.
This device has an electric field weakening source structure. Thus, in erasing data, it is possible to suppress the generation of electrons and holes resulting from a band-to-band tunnel in the vicinity of the channel region, thereby reducing the amount of holes injected into the tunnel oxide film
202
. As a result, it is possible to prevent the holes from being trapped in the tunnel oxide film
202
and it is also possible to prevent interface states from being generated, thereby reducing a variation in erasure characteristics and preventing a degradation of a retention margin and a write disturb margin.
FIG. 23
shows the cross section of a nonvolatile semiconductor memory device which is designed to shorten a write time or to reduce a write voltage by increasing a write efficiency. This device is disclosed by Nakao, et al. in Japanese Laid-Open Publication No. 7-115142.
The device shown in
FIG. 23
uses a semiconductor substrate
301
with a step
302
formed on the surface thereof. The surface of the semiconductor substrate
301
is divided by this step
302
into a surface region at a relatively high level (first surface region) and a surface region at a relatively low level (second surface region). A tunnel oxide film
303
, a floating gate
304
, a capacitive insulating film
305
and a control gate
306
are stacked in this order over the step
302
. In the surface of the semiconductor substrate
301
, a high-concentration source region
307
and a high-concentration drain region
308
, which have been doped with an impurity having a high concentration, are formed. A high-concentration impurity layer
309
having a small thickness of about 0.1 &mgr;m or less extends from the high-concentration drain region
308
along the side of the step
302
to reach the first surface region. Since the high-concentration impurity layer
309
functions as a drain region, a region between the high-concentration source region
307
and the high-concentration impurity layer
309
functions as a channel region. The floating gate
304
is formed so as to overlap the channel region and to cover the high-concentration impurity layer
309
.
In such a structure, since the floating gate
304
is located in the direction of velocity vectors of channel hot electrons, the channel hot electron injection efficiency is presumably increased.
Next, a method for fabricating the nonvolatile semiconductor memory device shown in
FIG. 23
will be described with reference to
FIGS. 24A
to
24
E.
First, as shown in
FIG. 24A
, an oxide film
311
is formed as a mask for forming a step in the semiconductor substrate
301
made of p-type silicon. Thereafter, a part of the oxide film
311
in the region where the step is to be formed is etched by a commonly used patterning technique. Then, the semiconductor substrate
301
is etched by using the oxide film
311
as a mask, thereby forming a step in the surface of the semiconductor substrate
301
. Subsequently, arsenic (As) ions are implanted into the whole of the step side region and the second surface region at a relatively high dose of about 1.0×10
15
cm
−2
and with an acceleration energy of about 20 keV. This

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