Nonvolatile semiconductor device and method of manufacturing sam

Details Nonvolatile semiconductor device and method of manufacturing sam Nonvolatile semiconductor device and method of manufacturing sam

1997-08-14

1998-11-17

Nelms, David

Static information storage and retrieval

Systems using particular element

Semiconductive

365104, 437 43, 357 235, G11C 1134

Patent

active

058386114

ABSTRACT:
A semiconductor memory device with a contactless array structure has bit-lines formed in a semiconductor substrate by diffusion of an impurity. Word-lines (control gates) are formed on the substrate so as to intersect the bit-lines. Floating gates are disposed in intersecting regions between the bit- and word-lines. Regions of higher resistance extend in parallel to the bit-lines located on both sides of a floating gates and located in an offset manner relative to the floating gate. A thick dielectric film is formed between the regions of higher resistance and word-lines. In this semiconductor memory device, a source side injection method with higher efficiency can be utilized for electron injection to a floating gate (programming) and thereby a lower programming voltage, less power consumption, and higher degree of integration are achieved.

REFERENCES:
patent: 5615152 (1997-03-01), Bergemont
patent: 5638327 (1997-06-01), Dallabora et al.
patent: 5666304 (1997-09-01), Hikawa et al.
patent: 5717636 (1998-02-01), Dallabora et al.
by M. Ohi et al., "An Asymmetrical Offset Source/Drain Structure for Virtual Ground Array Flash Memory with DINOR Operation", 1993 Symposium on VLSI Technology, The Japan Society of Applied Physics, the IEEE Electron Devices Society, May 1993, pp. 57 and 58.
by J. Esquivel et al., "High Density Contactless, Self Aligned Eprom Cell Array Technology", IEDM Technical Digest, Dec. 1986, pp. 592-595.

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