Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-20
2004-10-19
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000, C257S316000, C257S411000
Reexamination Certificate
active
06806532
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as a nonvolatile semiconductor memory device.
2. Description of the Prior Art
A conventional nonvolatile semiconductor memory device includes, as shown in
FIG. 13
, a drain
7
of n+ diffused layer and a source
8
of n+ diffused layer both formed in an upper region of a silicon substrate
1
. Also, a gate insulating layer
5
is formed between the drain
7
and the source
8
. As a gate electrode
21
is formed on the gate insulating layer
5
, the overall arrangement constitutes a memory transistor. Isolating oxide layers (Local Oxidation of Silicon: hereinafter referred to as LOCOS)
6
are formed over the drain
7
and the source
8
respectively. The gate insulating layer
5
in each memory transistor is disconnected over the isolating oxide layers (LOCOS)
6
. The gate insulating layer
5
has a multi-layer (Oxide layer/Nitride layer/Oxide layer: hereinafter referred to as ONO) structure consisting mainly of a silicon oxide layer
2
, a silicon nitride layer
3
, and a silicon oxide layer
4
. The nonvolatile semiconductor memory device of this type is generally known as an n-channel MOSFET (hereinafter referred to as NROM) (Boaz Eitan, et al., “Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?”, Extended Abstract of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 522-523 and U.S. Pat. No. 5,768,192).
The writing to the nonvolatile semiconductor device (NROM) will be now explained by referring to the relevant drawings. Memory transistors in the nonvolatile semiconductor device may be operated in two modes where data is recorded in the form of charges trapped in the silicon nitride layer
3
just above the drain
7
(the memory of Bit A) and in the silicon nitride layer
3
just above the source
8
(the memory of Bit B).
The memory of Bit A is explained. Referring to
FIG. 14A
, while the silicon substrate
1
is grounded and the drain
7
, the source
8
, and the gate electrode
5
are fed with 5 V, 0 V, and 10 V respectively, channel hot electrons are injected into the silicon nitride layer
3
directly on the drain
7
. The injected electrons are trapped in the silicon nitride layer
3
at its trapping level. The trapping of electrons at the trapping level is referred to as the writing of Bit A. For writing of Bit B, while the silicon substrate
1
is grounded and the drain
7
, the source
8
, and the gate electrode
5
are fed with 0 V, 5 V, and 10 V respectively as shown in
FIG. 14B
, channel hot electrons are injected into the silicon nitride layer
3
directly on the source
8
. The injected electrons are trapped at the trapping level in the silicon nitride layer
3
. The trapping of electrons at the trapping level is referred to as the writing of Bit B.
In a conventional nonvolatile memory, data is stored in the form of electrons trapped in the silicon nitride layer
3
directly on the drain
7
or the silicon nitride layer
3
on the source
8
. However, when the electrons trapped in the silicon nitride layer
3
directly on the drain
7
migrates in the silicon nitride layer
3
and are moved close to the source
8
, the density of electrons trapped in the silicon nitride layer
3
on the drain
7
will be decreased and thus data of Bit A will be lost. Simultaneously, data of Bit B in the source
8
may be replaced. Also, a reverse of this phenomenon will take place. More specifically, data of Bit A may be replaced by data of Bit B or vice versa or lost.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to form a nonvolatile memory semiconductor device where data in the form of electrons trapped in the silicon layer disposed directly on the source or the drain can hardly be lost or replaced by another data.
In accordance with one aspect of the present invention, there is provided a semiconductor device including a drain and a source, an insulating layer, and a gate electrode. The drain and the source are formed in an upper region of a semiconductor substrate. The insulating layer is formed on and between the drain and the source on the semiconductor substrate. The gate electrode is formed on the insulating layer. In addition, the insulating layer has an area arranged between the drain and the source at least on a channel region for interrupting the electron migration. The area may be called as the area interrupting the electron migration.
In other aspect of the present invention, the area interrupting the electron migration extends on the channel region in parallel with the both drain and source.
In further aspect of the present invention, the insulating layer has a multi-layer structure consisting mainly of a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.
In another aspect of the present invention, the area interrupting the electron migration includes a hydrogen injected region.
In a further aspect of the present invention, the area interrupting the electron migration includes a fluorine injected region.
In a still further aspect of the present invention, the area interrupting the electron migration comprises the silicon nitride layer extending discontinuously and the silicon oxide layer filling the discontinuous portions in the silicon nitride layer.
In accordance with one aspect of the present invention, there is provided a method of manufacturing a semiconductor device including the following steps:
S1: forming a drain and a source in an upper region of a semiconductor substrate;
S2: forming an insulating layer on and between the drain and the source on the semiconductor substrate;
S3: forming an area interrupting the electron migration in the insulating layer at least on a channel region between the drain and the source for interrupting the electron migration; and
S4: forming a gate electrode on the insulating layer.
In other aspect of the present invention, there is provided a method of manufacturing a semiconductor including the following steps:
S5: forming an insulating layer on a semiconductor substrate;
S6: forming a mask layer (e.g. silicon nitride layer) on the insulating layer
S7: patterning the mask layer;
S8: etching the insulating layer to form at least two apertures by using a pattern of the mask layer;
S9: implanting ions into the semiconductor substrate through the two apertures in the insulating layer to form injected regions in an upper region of the semiconductor substrate;
S10: heating and oxidizing the upper region of the semiconductor substrate through the two apertures to form isolating oxide layers;
S11: forming oxide layers on the isolating oxide layers to fill up the two apertures;
S12: removing the mask layer (e.g. silicon nitride layer) to leave desired portions of the oxide layers on the isolating oxide layers;
S13: forming side walls around each portion of the oxide layers on the isolating oxide layers;
S14: implanting ions into an exposed region of the insulating layer between the two side walls to form an ion injected region; and
S15: forming a word line on the exposed region of the insulating layer.
In further aspect of the present invention, the step of implanting an ion injected region employs hydrogen ions to be implanted.
In another aspect of the present invention, the step of implanting an ion injected region employs fluorine ions to be implanted.
In an aspect of the present invention, there is provided a method of manufacturing a semiconductor device including the following steps:
S5: forming an insulating layer on a semiconductor substrate;
S6: forming a mask layer (e.g. silicon nitride layer) on the insulating layer;
S7: patterning the mask layer;
S8: etching the insulating layer to form at least two apertures by using a pattern of the mask layer;
S9: implanting ions into the semiconductor substrate through the two apertures in the insulating layer to form injected regions in an upper region of the semiconductor substrate;
S10: heating and oxidiz
Le Thao X.
Pham Long
Renesas Technology Corp.
LandOfFree
Nonvolatile semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3313881