Nonvolatile random access memory device having transistor and ca

Static information storage and retrieval – Systems using particular element – Capacitors

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365180, 365177, 257 77, G11C 11401

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054652499

ABSTRACT:
A random access memory (RAM) cell in 6H-SiC having storage times when all bias is removed long enough to be considered nonvolatile. The nonvolatile random access memory (NVRAM) cell comprises a bit line, a charge storage device in silicon carbide, and a transistor in silicon carbide connecting the charge storage device to the bit line. The bipolar NVRAM cell has a bipolar transistor with a base region, an emitter region, and a floating collector region, wherein the charge storage device in the bipolar NVRAM is a p-n junction adjacent the floating collector region of the cell. The metal-oxide-semiconductor (MOS) NVRAM has a MOS field effect transistor (MOSFET) with a channel region, a source region, and a drain region, wherein the charge storage device in the MOS NVRAM is a MOS capacitor adjacent the drain region of the MOSFET.

REFERENCES:
patent: 3876992 (1975-04-01), Pricer
patent: 4183040 (1980-01-01), Rideout
patent: 4635083 (1987-01-01), Cooper, Jr.
patent: 4751201 (1988-06-01), Nottenburg et al.
patent: 4866005 (1989-09-01), Davis et al.
patent: 4875083 (1989-10-01), Palmour
patent: 4912063 (1990-03-01), Davis et al.
patent: 4912064 (1990-03-01), Kong et al.
patent: 4947218 (1990-08-01), Edmond et al.
patent: 4975750 (1990-12-01), Hayashi et al.
patent: 4981551 (1991-01-01), Palmour
Rutz, "Bistable Switch with Nonvolatile Memory States", IBM TDB, vol. 13, No. 11, Apr. 1971, pp. 3305-3306.
Dungan et al., "A Thermal-Generation-Limited Buried-Well Structure for Room-Temperature Gas Dynamic RAM's", EDL, vol. IEDL-8, 5 May 1987, pp. 243-245.
Bedair et al., "Extremely Low Leakage GaAs P-I-N Junctions and Memory Capacitors Grown by Atomic Layer Epitaxy", IEDL, vol. 11, No. 6, Jun. 1990, pp. 261-263.
"High Density Memories" by Peter M. Quinn, et al., ISSCC, Feb. 16, 1978.
"VLSI Fabrication Priciples" by Sorab K. Ghandhi, Native Oxide Films, pp. 400-401; no date.
"Proposed Process Modifications for Dynamic Bipolar Memory to Reduce Emitter-Base Leakage Current" by Ignor Antipov, Transactions On Electron Devices, vol. ED-27, No. 8, Aug. 1980, pp. 1649-1654.
"3-Dimensional Stacked Capacitor Cell For 16M and 64M Drams" by T. Eno, et al., IEEE, 1988; pp. 592-595.
"A Buried-Trench DRAM Cell Using A Self-aligned Epitaxy Over Trench Technology" by C. Lu, et al., IEEE, 1988, pp. 588-591.
"Memory II" by Thomas A. Longo, IEEE International Solid-State Circuits Conference, 1976, pp. 182-183.
"Cell Structures For Future Drams" by Hideo Sunami, Central Research laboratory, Hitachi Ltd. Kokubunji, Tokyo 185, Japan, IEEE, 1985, pp. 694-697.

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