Electrical computers and digital processing systems: support – Computer power control – Power sequencing
Reexamination Certificate
1994-08-09
2001-02-27
Auve, Glenn A. (Department: 2781)
Electrical computers and digital processing systems: support
Computer power control
Power sequencing
Reexamination Certificate
active
06195755
ABSTRACT:
FIELD OF INVENTION
This invention relates to the management of electrical power consumption in individual integrated circuits.
The invention is particularly useful, though not exclusively applicable, to CMOS integrated circuits where both control of the total power used by the integrated circuit and maintenance of state information is desirable.
BACKGROUND OF THE INVENTION
The management of the use of electric power within an electronic device has become extremely important. A device for electric power management as disclosed by Pardo/Webster in “Power Control Sequencer for Low Power and Battery Powered Applications,” U.S. patent application Ser. No. 08/099,942, Jul. 30, 1993 which generally:
1) determines when a function within an electronic device is idle,
2) saves pertinent information relative to the state of that function,
3) removes the power from those components that support the function,
4) determines when the function is to be reactivated,
5) reapplies power to the powered down components associated with the powered down function, and
6) restores the function to a defined state.
The principal advantages of the Power Control Sequencer (PCS) for management of electrical power over other methods is:
1) power is not applied to functional circuits which are performing no useful function, and
2) the PCS overcomes the inherent latch-up and loading problems associated with integrated circuits when one integrated circuit which has power applied has inputs and/or outputs connected to another integrated circuit which has its power removed.
The principal disadvantage of the Power Control Sequencer (PCS) for management of electrical power is:
1) state and other information electrically stored in the function are lost when power is removed from that function. Separate electronics are required to store any state or other information required for later use prior to removal of power, and to restore the information subsequent to the reapplicaton of power.
2) the parts of the invention which control latch-up and inter-intergrated circuit loading can become a significant design and power management problem in themselves as device complexity increases.
Webster and Pardo also disclosed a method for managing the use of power within individual integrated circuits in “Power Management Apparatus (PMA) for Integrated Circuit Application,” U.S. Pat. application Ser. No. 08/185,185, Jan. 21, 1994 which generally:
1) allows the power source of an integrated circuit function to be connected and disconnected on command,
2) connects the input/outputs of the integrated circuit function to external circuitry when the power source is connected to the integrated circuit function, and
3) isolates the input/outputs of the integrated circuit function from external circuitry when the power source is disconnected from the integrated circuit function in order to avoid external circuit loading, and the latch-up phenomena associated with electronics when the input/output nets of a powered-on device are directly connected to the input/output nets of a powered-off device.
4) the method generally solves problem #2 associated with the PCS by integrating the buffer and power control functions directly into each integrated circuit. The apparatus does not provide an improvement against problem #1 associated with the PCS.
As in the Power Control Sequencer, the principal disadvantage of the Power Management Apparatus for management of electrical power is:
1) state and other information electrically stored in the integrated circuit function are lost when power is removed from that integrated circuit function. Separate electronics are required to store any state or other information required for later use prior to removal of power, and to restore the information subsequent to the reapplicaton of power.
The capability to manage the use of power within an electronic device and within individual integrated circuits is important. Even with unclocked CMOS integrated circuits, small amounts of instantaneous power used consistently over a long period of time can added up to a significant amount of total power used. In the two aforeto mentioned Webster/Pardo patent applications, the general philosophy applied to power management is:
1) if a functional circuit is not powered-up, it uses essentially zero power for the time it is “off,” regardless of the length of that time.
2) efficient power management practice will power-on only those functional circuits then performing a useful function.
3) when the functional circuit ceases to perform its useful function, power will be removed from it.
In this patent application, Webster/Pardo recognize that certain functional circuits, once they have begun to operate, may enter a state wherein the functional circuit contains useful information while the functional circuit is itself not performing any other useful function other than the storage of that information. If power were completely removed as is defined in the aforeto mentioned patent applications of Webster/Pardo, then this information is lost when power is removed from the functional circuit. Webster/Pardo previously overcame the loss of information by moving the information out of the functional (integrated) circuit into a separate storage area prior to the removal of power.
This patent application describes an apparatus wherein the power to a functional circuit contained in an integrated circuit is not completely removed, but decreased such that the functional circuit is placed in a reduced power mode of operation. This is accomplished by controlling the voltage on integrated circuit's power input net and thereby varying the power used by the integrated circuit. The functional circuit retains all of the state properties it had possessed prior to the assertion of the reduced power mode. Use of the apparatus disclosed in this application eliminates the problem associated with the storage of state and other information in separate electronics external to the functional circuit prior to the removal of power, eliminates the latch-up phenomena associated with substrate reverse bias in the integrated circuit being operated with decreased power (power input net voltage reduced), and protects external circuitry from being overloaded by an integrated circuit operating with low voltage on its power input net. Substantial power savings are realized by functional circuits which incorporate a Nonvolatile Power Management Apparatus relative to power utilized by the same functional circuit without the Nonvolatile Power Management Apparatus.
The present invention creates a “Nonvolatile Power Management Apparatus (NPMA)” for integrated circuits. The NPMA is defined herein having several variations to the primary embodiment. The NPMA combines several electronic “means” in unique ways to perform power management. The NPMA draws from the PMA, replacing one of the PMA building blocks with a different building block. A NPMA changes the PMA function of “power switching means” to a “variable power source means.” The NPMA also incorporates the PMA concept of “signal switching means,” but with a broader definition. A “variable power source means” and “signal switching means” are combined with functional circuits on integrated circuit substrates to create several new types of integrated circuits which contain the NPMA.
The various embodiments of the NPMA provide the designer with design tools from which power management can be more easily accomplished relative to the prior art. Using the NPMA, power management can be accomplished at the individual integrated circuit level while retaining state and other information during the power management process. Electronic devices designed using the NPMA are simpler to generate, manufacture, and test. They would have a wider range of usefulness and would also be more reliable relative to a PMA or PCS designed into the same equipment. Most importantly, significant amounts of power can be saved in electronic devices which use the NPMA relative to the current state-of-the-art. The inventors firmly believe tha
Pardo Ehud
Webster Larry D.
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