Nonvolatile memory with write data latch

Details Nonvolatile memory with write data latch Nonvolatile memory with write data latch

1995-11-08

1997-03-25

Nelms, David C.

Static information storage and retrieval

Floating gate

365 63, 36518513, 36518525, 36518905, G11C 700

Patent

active

056151462

ABSTRACT:
The drain of a memory cell transistor is connected to a sub bit line of an EEPROM. The sub bit line is connected to a latch circuit through a connection transistor. The potential of the sub bit line which corresponds to the data stored in the memory cell transistor is latched by the latch circuit. With this potential latching operation, the potential of the sub bit line is held at a predetermined value corresponding to the data stored in the memory cell.

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