Nonvolatile memory with data write circuitry to reduce write err

Details Nonvolatile memory with data write circuitry to reduce write err Nonvolatile memory with data write circuitry to reduce write err

1988-11-21

1991-05-14

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365185, G11C 700

Patent

active

050162187

ABSTRACT:
In a nonvolatile memory of the present invention, a write circuit is connected between bit lines and a write-enable voltage terminal and has at least two write MOS transistors connected to each other in a serial manner. Since at least two write MOS transistors are connected in a serial manner, a punch-through effect is reduced even if noises occur in a write voltage system. Even in the case where a punch-through effect occurs due to the presence of a power source and transistors, a voltage on the bit line is reduced, thus preventing a write error from occurring relative to the memory cell transistors.

REFERENCES:
patent: 4710900 (1987-12-01), Higuchi
patent: 4733371 (1988-03-01), Tenada et al.
patent: 4761764 (1988-08-01), Watanabe
patent: 4843594 (1989-06-01), Tanaka et al.
patent: 4905197 (1990-02-01), Urai
Atsumi, S. et al., "Fast Programmable 256K Read Only Memory with On Chip Test Circuits," IEEE Transactions on Electron Devices, vol. ED-32, No. 2, published Feb., 1985.
"A 25-ns 16K CMOS PROM Using a Four-Transistor Cell and Differential Design Techniques" by Pathak et al., IEEE Journal of Solid-State Circuits, vol. SC20, No. 5, Oct. 1985, pp. 964-970.
"A 19-ns 250-mW CMOS Erasable Programmable Logic Device" by Pathak et al., IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 775-784.

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