Nonvolatile memory with a write protection circuit

Details Nonvolatile memory with a write protection circuit Nonvolatile memory with a write protection circuit

1996-04-23

1997-09-16

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

36518905, 365191, 365195, 365193, G11C 700, G11C 800

Patent

active

056687605

ABSTRACT:
A nonvolatile memory includes a memory array and a control circuit having a command latch and a command decoder. The control circuit receives an output enable signal and a write enable signal to control memory operations of the memory array in accordance with a command latched into the command latch via the command decoder. A write protection circuit is also provided that disables the command latch and the command decoder when the output and write enable signals are both active. The protection circuit includes a pulse generator that generates a reset signal to reset the command latch to the read array state and a control logic that causes the pulse generator to assert the reset signal when an output enable signal and a write enable signal of the memory are both active until after the write enable signal has been forced internally inactive and the command latch closed.

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patent: 5463581 (1995-10-01), Koshikawa
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patent: 5532961 (1996-07-01), Mori et al.
patent: 5555209 (1996-09-01), Smith et al.
patent: 5559738 (1996-09-01), Mizobata et al.
patent: 5600606 (1997-02-01), Rao
patent: 5604714 (1997-02-01), Manning et al.

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