Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2001-07-26
2002-09-24
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
C365S189050, C365S230080
Reexamination Certificate
active
06456538
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims, under 35 U.S.C. §119, the benefit of Korean Patent Application No. 2000-45998, filed on Aug. 8, 2000, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory and a system having nonvolatile memories, and more particularly, to a nonvolatile memory, a system having nonvolatile memories, and a data read method of the system that performs a data read operation by interleaving consecutively a plurality of the nonvolatile memories.
2. Description of Related Art
In general, systems having a plurality of memories include a controller to control its operation. However, since such systems use common signal lines to transmit data between the memories and the controller, it is very important in system performance to interleave operation of many memories.
Conventional systems having a plurality of the nonvolatile memories can interleave a plurality of the nonvolatile memories by having a “don't care” interval during a write or an erase operation. During a read operation, however, it is impossible to interleave a plurality of the nonvolatile memories.
FIG. 1
is a block diagram illustrating a system having a plurality of the nonvolatile memories according to the prior art. As shown in
FIG. 1
, the system includes a controller
10
and a plurality of nonvolatile memories
20
-
1
to
20
-n. Control signals CLE, ALE, WEB and REB are transmitted from the controller
10
to the nonvolatile memories
20
-
1
to
20
-n through control signal lines
30
. Inverted chip enable signals CEB
1
to CEBn are transmitted from the controller
10
to the nonvolatile memories
20
-
1
to
20
-n through inverted chip enable signal lines
32
. Ready/busy signals RBB
1
to RBBn are transmitted from the controller
10
to the nonvolatile memories
20
-
1
to
20
-n through ready/busy signal lines
34
. Input/output data IO
0
to IOn are transmitted from the controller
10
to the nonvolatile memories
20
-
1
to
20
-n through data input/output lines
36
.
The signal CLE is a command latch enable signal that discriminates whether the inputted data are a command. The signal ALE is an address latch enable signal ALE that discriminates whether the inputted data are an address. The signal WEB is an inverted write enable signal that latches all inputted data that are written ( whether a command, an address, or the like). The signals CEB
1
to CEBn are inverted chip enable signals that enable a plurality (n in number) of the nonvolatile memories
20
-
1
to
20
-n. The signal REB is a read enable signal that enables a read operation. The signals IO
1
to IOn are data that are inputted/outputted to/from the nonvolatile memories
20
-
1
to
20
-n. The signals RBB
1
to RBBn are ready/busy signals that indicate internal operation state of the nonvolatile memories
20
-
1
to
20
-n.
FIG. 2
is a block diagram illustrating a configuration of an embodiment of the nonvolatile memory
20
-
1
of FIG.
1
. As shown in
FIG. 2
, the nonvolatile memory
20
-
1
includes a memory cell array
40
, a row decoder
42
, a column decoder
44
, a control signal generating circuit
46
, a page buffer
48
, a data input/output gate
50
, and a data input/output buffer
52
. The memory cell array
40
includes a plurality of memory cells (not shown) for storing data.
An operation of the nonvolatile memory
20
-
1
is explained below in detail. The row decoder
42
decodes a row address X, operating under the control of the control signal generating circuit
46
. This selects a plurality of word lines (not shown) of the memory cell array
40
.
The column decoder
44
decodes a column address Y, operating under the control of the control signal generating circuit
46
, and selects the data input/output gate
50
. The page buffer
48
stores byte data by one page size, in response to output signals from the column decoder
44
The byte data are inputted through the data input/output gate
50
during the write operation and that are outputted from the memory cell array
40
during the read operation. The data input/output gate
50
transmits data of one page size in byte unit to the data input/output buffer
52
in response to output signals from the column decoder
44
. The data input/output buffer
52
buffers data of one page size that are inputted from an external portion, operating under the control of the control signal generating circuit
46
, and then outputs to the data input/output gate
50
during the write operation. The data input/output buffer
52
buffers byte data outputted from the data input/output gate
50
, outputs the byte data to an external portion during the read operation.
During the write operation, the nonvolatile memory
20
-
1
stores data of one page size in byte unit inputted from an external portion in the page buffer
48
. Then data of one page size stored in the page buffer
48
are transferred to the memory cell array
40
.
Conversely during the read operation, data of one page size that are stored in the memory cell array
40
are transferred to the page buffer
48
. Then, data of one page size stored in the page buffer
48
are outputted in byte unit through the data input/output gate
50
and the data input/output buffer
52
.
That is, the nonvolatile memory
20
-
1
transfers data to the memory cell array
40
, or transfers data to the external portion through the data input/output gate
50
and the data input/output buffer
52
. In the process, data become stored in the page buffer
48
.
The nonvolatile memory
20
-
1
generates the ready/busy signal RBB having a logic “high” level when control signals, an address and data are inputted from an external portion. Further, the nonvolatile memory
20
-
1
generates the ready/busy signal RBB having a logic “low” level when performing an operation for reading data from the memory cell array
40
to the page buffer
48
, and also when performing an operation for write and erase data from the page buffer
48
to the memory cell array
40
.
FIG. 3
is a block diagram illustrating an internal inverted chip enable signal generating circuit
59
in the nonvolatile memory
20
-
1
according to the prior art. Circuit
59
includes a CEB buffer
60
, a WEB disable detecting circuit
62
, a REB disable detecting circuit
64
, a program command detecting circuit
66
, an erasing command detecting circuit
68
, a read command detecting circuit
70
, a PGM DNT signal generating circuit
72
, a ERS DNT signal generating circuit
74
, a RD DNT signal generating circuit
76
, a RBB busy detecting circuit
78
, a NOR gate NOR
1
, a NAND gate NAND
1
, and an inverter I
1
.
An operation of the inverted chip enable signal generating circuit is explained below in detail. The CEB buffer
60
buffers the external inverted chip enable signal CEB that is applied from an external portion, and then outputs it. The WEB disable detecting circuit
62
detects a transition of an inverted write enable signal WEB to a logic “high” level, and then generates the WEB disable detecting signal. The REB disable detecting circuit
64
detects a transition of the inverted read enable signal REB to a logic “high” level, and then generates the REB disable detecting signal. The program command detecting circuit
66
generates a program command detecting signal when a program command
80
H is applied. The erase command detecting circuit
68
generates an erase command detecting signal when an erase command
60
H is applied. The read command detecting circuit
70
generates a read command detecting signal when read commands
00
H,
01
H and
50
H are applied. The RBB busy detecting circuit
78
detects a busy state of the ready/busy signal RBB and generates a RBB busy detecting signal.
In addition, the PGM DNT signal generating circuit
72
generates a program “don't care” signal PGM DNT having a logic “high” level when the program command detecting signal and the WEB disable detecting signal are generated. The ERS DNT
Choi Young-Joon
Song Seung-Taek
Lam David
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co Ltd.
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