Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-07
2001-01-09
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000
Reexamination Certificate
active
06172393
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. More particularly, the present invention relates to a nonvolatile memory having a contactless array structure, in which an impurity diffusion layer is used as a bit line, and a method of manufacturing the nonvolatile memory.
2. Description of the Related Art
FIGS. 1 and 2
show a flash memory having a split gate type of contactless array structure described in Japanese Laid Open Patent Application (JP-A-Heisei 8-97304).
As shown in
FIG. 1
, an n-type impurity diffusion layer
105
constituting a source/drain region, a silicon oxide film
106
formed by oxidizing a surface of a p-type silicon substrate
101
, a floating gate
108
, a control gate
113
also serving as a split gate, a silicon oxide film
107
, a silicon oxide film
112
and an inter-gate insulating film
114
are formed in a p-type silicon substrate
101
.
The silicon oxide film
107
is formed between the floating gate
108
and the p-type silicon substrate
101
to serve as a tunneling insulating film. The silicon oxide film
112
constitutes a gate insulating film in a split gate region. The inter-gate insulating film
114
is formed between the control gate
113
and the floating gate
108
.
FIG. 1
shows a case in which the three-layer structure of ONO is used as the inter-gate insulating film
114
. However, a single layer structure of the silicon oxide film may be used.
As shown in
FIG. 2
(
FIG. 1
is a section view taken on the line A-A′ of FIG.
2
), the n-type impurity diffusion layer
105
also serves as a bit line. The control gate
113
also serves as a word line. In this way, the type in which the impurity diffusion layer is used as the bit line is referred to as a contactless array. Since the impurity diffusion layer is used as the bit line in the contactless array structure, the creation of a hyperfine structure is easier than that in a contact array structure which requires a single wiring contact per cell.
Operations of the flash memory shown in
FIG. 1
will be described below.
Here, a write state is assumed to be a low threshold voltage state (an electron emission state), and an erase state is assumed to be a high threshold voltage state (an electron injection state).
In the writing operation, for example, −8 V is applied to the control gate
113
, 5 V is applied to the drain (the n-type impurity diffusion layer
105
on the right side in FIG.
1
), the source (the n-type impurity diffusion layer
105
on the left side in
FIG. 1
) is opened, and the substrate
101
is grounded. Then, the electrons are drawn from the floating gate
108
to the drain through F-N (Fowler Nordheim) tunneling. This leads to the reduction of a threshold voltage of a memory transistor.
In the erasing operation, a high voltage, for example, 16 V is applied to the control gate
113
. Then, the drain
105
, the source
105
and the substrate
101
are all grounded. The electrons are drawn from the substrate
101
or the drain
105
to the floating gate
108
through the F-N tunneling.
Under this condition, a film thickness of the silicon oxide film
112
in the split gate region is sufficient, which prevents an F-N tunnel current from flowing to the split gate. Thus, the application of the high voltage to the control gate
113
does not cause the silicon oxide film
112
in the split gate region to be deteriorated.
Also, the reading operation is performed such that 3 to 5 V is applied to the control gate
113
. Approximately 1 V is applied to the drain
105
. The source
105
and the substrate
101
are grounded. Then the presence or absence of drain current is detected.
As mentioned above, the flash memory shown in
FIG. 1
uses the impurity diffusion layer
105
as the bit line. Thus, the creation of the hyperfine structure is easier than that with the contact array structure which requires the single wiring contact per cell.
However, in order to further promote the creation of the hyperfine structure, it is necessary to prevent the diffusion of the impurity of the impurity diffusion layer
105
in a lateral direction, namely, in a gate direction from causing a short channel effect. Therefore it is inevitable to reduce the dose amount of the impurity doped and decrease a temperature at an activating process. As a result, the impurity diffusion layer
105
serving as the bit line becomes narrow in width and becomes shallow in a depth direction. Thus, a resistance of the bit line becomes higher associated with a smaller cross-sectional region. Hence, a current flowing through the bit line becomes smaller. As a result, if trying to provide a sufficient current flow through the cell such that an access speed of the cell is not slow, it is necessary to reduce the number of cells connected to the bit line.
Moreover, if the resistance of the bit line becomes larger as mentioned above, a length of the bit line connected to the single contact is limited, which reduces the number of memory cells connected to the single contact. Accordingly, the number of contacts in the flash memory as a whole is increased, which results in a problem that the creation of the hyperfine structure can not be sufficiently achieved.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a contactless array type of a nonvolatile memory which can reserve a sufficient ON current, without increasing a resistance, even if a width of a bit line is reduced to create a hyperfine structure. Moreover, according to the present invention, it can be held to a sufficiently small resistance. Thus, many memory cells can be connected to the single contact. Hence, the number of contacts can be reduced. Therefore, it is possible to attain the creation of the further hyperfine structure.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-described problems of the conventional nonvolatile semiconductor memory. That is, this nonvolatile memory having contactless array structure can reserve sufficient ON current, without increasing resistance, even if width of bit line is reduced and creation of hyperfine structure is tried, and method of manufacturing nonvolatile memory.
In order to achieve an aspect of the present invention, a nonvolatile memory includes a first conductive type of semiconductor region; and a second conductive type of impurity diffusion layer which is formed by doping into a predetermined region of the semiconductor region, impurity of the second conductive type that differs from the first conductive type, the impurity diffusion layer being used as a bit line, wherein the impurity diffusion layer has a specific layer in which an impurity density is substantially equal to or higher than 1×10
18
cm
−3
, and wherein B>A where A is a diffusion length in a lateral direction from the predetermined region and B is a thickness of the specific layer in a depth direction.
In this case, a thickness of the impurity diffusion layer in a depth direction is larger than half a width of a surface portion of the impurity diffusion layer.
Also in this case, the thickness of the specific layer in the depth direction of the impurity diffusion layer is substantially equal to or higher than 0.25 &mgr;m.
Further in this case, the impurity diffusion layer has, in a predetermined position of the impurity diffusion layer in a depth direction, a maximum impurity density portion in which the impurity density of the impurity diffusion layer is maximum.
In order to achieve another aspect of the present invention, the maximum impurity density portion is substantially provided in a depth of 0.05 &mgr;m or more from a surface portion of the impurity diffusion layer.
In this case, a side close to a surface portion of the impurity diffusion layer is lower in impurity density of the impurity diffusion layer than a side away from the surface portion of the impurity diffusion layer.
Also in this case, in the impurity diffusion
Hisamune Yoshiaki
Kanamori Kohji
Meier Stephen D.
NEC Corporation
Scully Scott Murphy & Presser
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