Nonvolatile memory device with test mechanism

Details Nonvolatile memory device with test mechanism Nonvolatile memory device with test mechanism

2006-04-28

2008-08-19

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S154000

Reexamination Certificate

active

07414903

ABSTRACT:
A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.

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