Nonvolatile memory device with parallel and serial...

Details Nonvolatile memory device with parallel and serial... Nonvolatile memory device with parallel and serial...

2005-05-17

2005-05-17

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S201000, C712S029000

Reexamination Certificate

active

06894914

ABSTRACT:
An architecture of a nonvolatile memory device, though not requiring dedicated pins and by introducing circuit modifications that require a negligible additional silicon area in the serial interface, allows a selection between at least two different serial communication protocols, thus multiplying the occasions of employment of the same device. The selection of one or of the another serial communication protocol is carried out by setting, during the testing on wafer (EWS) of the devices being fabricated, a certain UPROM cell of the array of UPROM cells that is normally present in a standard nonvolatile memory device for setting during the fabrication the characteristics of ATD, redundancy and other functions of the memory device. Alternatively, the customer can make the selection by placing an appropriate signal level on a specified pin of the memory device.

REFERENCES:
patent: 5896534 (1999-04-01), Pearce et al.
patent: 6311263 (2001-10-01), Barlow et al.

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