Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2003-04-10
2004-09-14
Lam, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S171000, C365S210130
Reexamination Certificate
active
06791869
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile memory device and more particularly to a nonvolatile memory device with memory cells characterized in that a passing current in reading data changes depending on a level of binary stored data.
2. Description of the Background Art
Recently, an MRAM (Magnetic Random Access Memory) device has attracted attention as a new-generation nonvolatile memory device. The MRAM device is a nonvolatile memory device using a plurality of magnetic thin films formed in a semiconductor integrated circuit to store data nonvolatally and allowing random access for each of magnetic thin films. In particular, in recent years, a magnetic thin film making use of a magnetic tunnel junction (MTJ) is used as a memory cell to dramatically improve the performance of the MRAM device, as reported for example in a reference such as “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, Roy Scheuerlein et al., (2000 IEEE ISSCC Digest of Technical Papers, TA7.2).
A memory cell having a magnetic tunnel junction (referred to as a “MTJ memory cell” hereinafter) can be configured with an MTJ element and an access element (for example a transistor) and thus is advantageous in high integration. An MTJ element has a magnetic layer that can be magnetized in a direction corresponding to an applied magnetic field. An MTJ memory cell stores data by taking advantage of the characteristics of an electric resistance (junction resistance) in the MTJ element that changes according to a magnetization direction of the magnetic layer.
To read stored data in an MTJ memory cell, it is necessary to sense an electric resistance difference corresponding to a stored data level. Specifically, data is read based on a passing current in the MTJ memory cell that changes according to an electric resistance (that is stored data).
However, the electric resistance of the MTJ element is generally on the order of a few tens of kilohms (k&OHgr;: 10
3
&OHgr;) and an electric resistance difference resulting from the difference of stored data levels is approximately 20-30% thereof Furthermore, the aforementioned passing current is on the order of microampere (&mgr;A: 10
−6
A) as the voltage applied at the time of a data read is suitably about 0.5V in consideration of the reliability of the MTJ element.
In an array configuration allowing one-bit data to be stored for each MTJ memory cell, it is necessary to compare a passing current of one MTJ memory cell selected for a data read with a prescribed reference current for reading. In such an array configuration, while a high integration can be attained by reducing the area per bit, it is necessary to sense a current with high accuracy as described above, resulting in a likelihood that a data read accuracy is decreased with a varied current level resulting from manufacturing variations.
Therefore, in an application that strongly requires the reliability of stored data, as introduced in the aforementioned reference, it is desirable to employ an array configuration that allows one-bit data to be stored with two MTJ memory cells in which complimentary data is written. However, since such an array configuration prevents a high integration, sufficient performance cannot be obtained in an application having a priority in a stored data capacity.
While the important property is different depending on the application of the memory device in this way, different array configurations employed depending on the application incur a complicated design and manufacturing cost, which adversely affects the cost. This problem becomes conspicuous particularly in the case where the MRAM device is incorporated into a system LSI (Large Scale Integrated circuit) configured with a plurality of function blocks having different applications.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a configuration of a nonvolatile memory device having a configuration capable of switching the number of memory cells required for storing one bit including the same.
A nonvolatile memory device in accordance with the present invention includes: a memory cell array having a plurality of memory cells arranged in a matrix, the memory cell having a passing current in reading data changed in first and second states respectively in accordance with levels of binary stored data; an access control circuit for switching access to the plurality of memory cells based on an input address between a first mode in which each of the plurality of memory cells stores one-bit data and a second mode in which each pair of two of the plurality of memory cells stores one-bit data; a data read circuit reading data from a memory cell of the plurality of memory cells that is selected to be accessed by the access control circuit; and a data write circuit writing data into the memory cell of the plurality of memory cells that is selected to be accessed.
Therefore the main advantage of the present invention is in that the number of memory cells required for one-bit storage can be switched in a common array configuration in the nonvolatile memory device. Therefore it is possible to flexibly handle both of an application having a priority in a data capacity and an application having a priority in data reliability without changing an array configuration.
A nonvolatile memory device in accordance with another configuration of the present invention includes: a plurality of memory cells having a passing current in reading data changed in first and second states respectively in accordance with levels of binary stored data; and a plurality of dummy cells provided to be compared with the plurality of memory cells in reading data and having same characteristic as the plurality of memory cells, wherein at least ones of the plurality of dummy cells are respectively set to the first and second states. The nonvolatile memory device further includes a data read circuit, based on access to a selected memory cell selected to be accessed of the plurality of memory cells and to the plurality of dummy cells, reading the stored data from the selected memory.
In such a nonvolatile memory device, in a memory cell array configuration having a dummy memory cell having characteristics similar to those of a normal cell, data can be read with reference to dummy memory cells having characteristics similar to those of memory cells respectively storing binary levels. As a result, a simplified manufacturing process and stabilized memory cell characteristics result because of the continuity in cell structures and in addition a data read accuracy can be improved.
A nonvolatile memory device in accordance with yet another configuration of the present invention includes: a plurality of memory cell blocks; and a data read circuit provided to be shared by the plurality of memory cell blocks. Each of the plurality of memory cell blocks includes a plurality of memory cells having a passing current in reading data changed in first and second states respectively in accordance with levels of binary stored data, and a plurality of dummy cells provided to be compared with the plurality of memory cells in reading data and having same characteristics as the plurality of memory cells, wherein one of the plurality of memory cells is selected as a memory cell from which data is to be read in one of the plurality of memory cell blocks. The data read circuit reads the stored data from the memory cell from which data is to be read based on respective access to the memory cell from which data is to be read and to one of the plurality of dummy memory cells included in another one of the plurality of memory cell blocks.
In such a nonvolatile memory device, a selected memory cell from which data is to be read and a dummy memory cell to be compared with the selected memory cell respectively belong to different memory cell blocks. Therefore the integration in each memory cell block can be improved without incurring complicated control of the c
Burns Doane Swecker & Mathis L.L.P.
Lam David
Renesas Technology Corp.
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