Nonvolatile memory device including multi-ECC circuit

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371 211, G06F 1110

Patent

active

054694507

ABSTRACT:
A nonvolatile memory device containing sub memory arrays and distinct associated peripheral sub array circuits containing error checking and correction circuits that are similarly positioned according to the sub array. The memory device is configured so that a single mask change allows the device to be manufactured as a normal mode device or a page mode device.

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patent: 4878220 (1989-10-01), Hashimoto
patent: 4937830 (1990-06-01), Kawashima et al.
patent: 5056089 (1991-10-01), Furuta et al.
patent: 5313425 (1994-05-01), Lee et al.

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