Nonvolatile memory device having bulk bias contact structure...

Details Nonvolatile memory device having bulk bias contact structure... Nonvolatile memory device having bulk bias contact structure...

2000-08-29

2002-11-19

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270

Reexamination Certificate

active

06483749

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory device and a method of fabricating the same, and more particularly, to a non-volatile memory device having a bulk bias contact structure in a cell array region.
2. Description of the Related Art
Non-volatile memory devices are widely used for computers or memory cards because the non-volatile memory devices retain information stored in their memory cells even when no power is supplied.
Phenomena affecting the operating characteristics of non-volatile memory devices will be described with reference to
FIG. 1
which is a partially-magnified circuit diagram of non-volatile memory devices. When a cell indicated by reference character A is to be selectively programmed, a program voltage V
PG
, for example, 10 to 15 V, is applied to a selected word line WL
1
which is connected to the cell A, and a voltage of about 5 V is applied to a selected bit line BL
1
which is connected to the cell A. A non-selected bit line BL
2
is connected to a cell that is adjacent to the selected cell A and shares the word line WL
1
with the selected cell A. The non-selective bit line BL
2
is floated. Also, a non-selected word line WL
2
is connected to a cell B that is adjacent to the selected cell A and shares the bit line BL
1
to which about 5 V is applied, with the selected cell A. The non-selected word line WL
2
is grounded. When the cell A is selectively programmed as described above, an electrical field in the channel region under the gate of the selected cell A remarkably increases in a pinch-off region around the drain of the selected cell A, so that electrons within the channel are accelerated by this strong electrical field and easily achieve in a high energy state. The electrons in a high energy state collide with a silicon lattice in a bulk region, generating a plurality of electron-hole pairs. Some electrons with high energy, among electrons and holes, generated by impact ionization, are injected into a floating gate via a tunnel oxide film by a gate electrical field, and the other electrons, i.e., most of the electrons, are led to the drain by a strong drain electrical field, and become part of the drain current. At this time, holes are pushed in the opposite direction to the electrons by the drain electrical field, and flow into a source terminal or bulk terminal via a depletion layer or a bulk region under a channel. Therefore, hole current, that is, bulk current I
BULK
, flows via the drain of the selected cell A and a bulk region. The bulk current I
BULK
increases a bulk voltage due to bulk resistance R
BULK
. When a bulk voltage becomes 0.6 V or more due to a large bulk resistance R
BULK
, a p-n junction between a source region, which is a ground node, and a substrate is forward biased, and thus undesired forward current is generated, thereby causing a snap back phenomenon in which cell current rapidly increases. Hence, cells may abnormally operate, or the junctions of cells may be destroyed by excessive current.
Meanwhile, a voltage V
FG
which is induced in the floating gate of the non-selected cell B is expressed by Equation 1 using a cell equivalent circuit shown in FIG.
2
:
V
FG
=(
C
D
×V
D
)+(
C
IPO
+C
D
+C
B
+C
S
)  (1)
wherein C
IPO
is the capacitance between a control gate and a floating gate, C
D
is the capacitance between the floating gate and drain, C
S
is the capacitance between the floating gate and source, C
B
is the capacitance between the floating gate and a bulk region, and V
D
is a voltage which is applied to the drain, i.e., a voltage which is applied to a bit line. Equation 1 refers to the case in which the control gate voltage V
CG
, the source voltage V
S
and the bulk voltage V
B
of the non-selected cell B are assumed to be 0 V.
It can be seen from Equation 1 and
FIG. 2
that the voltage V
FG
which is induced in the floating gate of the non-selected cell B is proportional to a voltage which is applied to the bit line BL
1
. If the non-selected cell B is an over-erased cell having a threshold voltage of a predetermined level or less (about 1 V), when a voltage of about 5 V is applied to the bit line BL
1
to program the cell A, a predetermined voltage is induced in the floating gate of the non-selected cell B, which may turn on the cell B. This is referred to as a drain turn on (DTO) phenomenon which causes leakage current, i.e., drain turn on current I
DTO
, to flow from the bit line BL
1
into a common source line CSL via the cell B. Once the cell B is turned on by the DTO phenomenon, the voltage of the bit line BL
1
is reduced. This causes difficulty in programming the selected cell A. In addition, the DTO current I
DTO
increases with an increase in the number of non-selected cells connected to a bit line. Also, the DTO phenomenon becomes more serious as the bulk voltage is increased by the bulk current IBULK in the selected cell A.
In order to solve the above problem, a bulk bias contact structure is formed to prevent a bulk voltage from increasing by discharging current which flows into the bulk region of cell transistors by applying a bias voltage to the bulk region. As shown in
FIGS. 3 and 4
, a conventional bulk bias contact is formed in the shape of a guard band
3
that surrounds a cell array region
1
. Alternatively, as shown in
FIGS. 5 and 6
, the conventional bulk bias contact may be formed in the shape of a bulk bias contact structure
5
on peripheral circuit regions corresponding to four corner regions of the cell array region
1
or corresponding to two corner regions among the four comer regions of the cell array region
1
. The bulk bias contact structure
5
can solve the defect of the guard band
3
which increases the area of the entire chip, because of its wide layout area. However, in unit cells which are distant from the bulk bias contact structure
5
, a large amount of bulk resistance is exhibited because of the long discharge path of the bulk current. Thus, the discharge effect of the bulk current is reduced, and the discharge effect of the bulk current is not uniform with respect to the position of unit cells.
A bulk bias contact structure, a guard band, an electro-static discharge prevention bulk bias contact structure, or the like have been formed in the active region of the peripheral circuit regions, in addition to the bulk bias contact structure in the cell array region for preventing the bulk voltage therein from being increased. The bulk bias contact structure maintains the bulk voltage of peripheral circuit regions at or below a predetermined voltage. The guard band prevents a latch-up phenomenon, or the like, which occurs between transistors for peripheral circuits.
As shown in
FIG. 7
, conventional bulk bias contact structures for maintaining the bulk voltage in a cell array region or peripheral circuit region at or below a predetermined voltage, are formed in the active region between isolation films
30
′ which are formed in the peripheral circuit regions on a semiconductor substrate
10
. Specifically, a region
40
doped at high concentration with impurities of a conductivity type that is the same as the conductivity type of the impurities of a bulk region, is exposed. And a contact hole between interlayer dielectric layers
34
′ is filled with a metal film pattern
50
, thereby completing the formation of the bulk bias contact structure. In order for the bulk bias contact structure to have a sufficient contact area, the area of the active region must be increased in consideration of the so-called bird's beak phenomenon in which the isolation films
30
′ grow toward the active region, upon layout. That is, in
FIG. 7
, the length of an actually-formed active region is d
1
, but the active region must be increased to a length of d
2
upon layout. Therefore, an active region of a predetermined length d
2
or greater is required to complete the bulk bias contact structure. As a result, the area of the entire chip increases by th

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