Nonvolatile memory device and semiconductor device

Details Nonvolatile memory device and semiconductor device Nonvolatile memory device and semiconductor device

2006-08-01

2006-08-01

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185180, C365S189090

Reexamination Certificate

active

07085157

ABSTRACT:
A method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 ìA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 ìA to flow a current in the memory cell.

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