Nonvolatile memory device

Details Nonvolatile memory device Nonvolatile memory device

2003-03-19

2004-10-26

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S326000

Reexamination Certificate

active

06809374

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a nonvolatile memory device, and relates more specifically to an improved metal-oxide-nitride-oxide-semiconductor (MONOS) memory device.
2. Description of the Related Art
One type of nonvolatile memory device is the metal-oxide-nitride-oxide-semiconductor (MONOS) memory device. One characteristic of a MONOS memory device is that the gate insulation layer between the channel region and control gate is a silicon oxide-silicon nitride-silicon oxide layer, and electric charges are trapped in the silicon oxide layer.
FIG. 6
is a partial sectional drawing of a MONOS type nonvolatile memory device according to the related art. In a MONOS type memory cell
100
the source region
101
a
and drain region
101
b
are formed in the semiconductor substrate
101
separated by a channel formation region disposed therebetween. A control gate (CG)
103
is formed over the channel region through an intervening gate insulation layer
104
. The gate insulation layer
104
has three layers, a first layer
104
a
that is a silicon oxide layer formed on the semiconductor substrate
101
, a second layer
104
b
that is a silicon nitride layer formed on the first layer
104
a
, and a third layer
104
c
that is a silicon oxide layer formed on the second layer
104
b
. The gate insulation layer
104
is structured to have a trap level in the second layer
104
b.
With this memory device, electrons hopping into the first layer
104
a
are trapped at the trap level of the second layer
104
b
. Electrons that enter and are trapped at the trap level cannot easily escape from the trap level, and thus stabilize.
Because electrons, or more specifically negatively charged particles, are held in the gate insulation layer
104
, and more precisely in the second layer
104
b
, at this time, the threshold value of the gate insulation layer
104
rises compared with the initial level. Whether or not data was written is determined by detecting change in this threshold value, and operation as a memory device is thus achieved.
Japanese Patent Laid-Open Publications (kokai) 2001-102466 and 2001-148434, and U.S. Pat. No. 6,255,166B1 teach a nonvolatile memory device of a so-called “split gate” type as an improvement of this MONOS type memory device.
FIG. 7
shows a split-gate nonvolatile memory device according to the related art. The nonvolatile memory device shown in
FIG. 6
stores one bit of data in one memory cell, but the split-gate memory device shown in
FIG. 7
can store two bits of data in one memory cell.
In
FIG. 7
a first impurity region (n-type)
201
a
and a second impurity region (n-type)
201
b
are formed in a p-type semiconductor substrate
201
separated by a channel formation region therebetween. This split gate memory cell
200
has a word gate (denoted “WG” in the figures)
203
formed on the semiconductor substrate
201
through an intervening first gate insulation layer
202
. A first control gate (denoted “LCG” in the figures)
204
and a second control gate (denoted “RCG” in the figures)
205
are formed as sidewalls on opposite sides of the word gate WG
203
. A second gate insulation layer
206
a
is disposed between the bottom of the first control gate LCG
204
and semiconductor substrate
201
. A first side insulation layer
207
a
is disposed between the side of first control gate LCG
204
and word gate WG
203
. A third gate insulation layer
206
b
is likewise disposed between the bottom of second control gate RCG
205
and the semiconductor substrate
201
, and a second side insulation layer
207
b
is disposed between the side of second control gate RCG
205
and the word gate WG
203
.
The second and third gate insulation layers
206
a
and
206
b
, and the first and second side insulation layers
207
a
and
207
b
have three layers, a first layer that is a silicon oxide layer formed on the semiconductor substrate
201
, a second layer that is a silicon nitride layer formed on the first layer, and a third layer that is a silicon oxide layer formed on the second layer.
Compared with the memory device shown in
FIG. 6
, the split gate memory device shown in
FIG. 7
is more complex structurally, but is a symmetrical structure that can record two bits.
Writing to the above split gate memory device is described first below using by way of example for simplicity writing to the second control gate RCG
205
side of this memory cell
200
.
A specific voltage is applied to the second impurity region (drain region)
201
b
, word gate WG
203
, first control gate LCG
204
, and second control gate RCG
205
. Of the electrons that move from the first impurity region (source region)
201
a
to the drain region
201
b
, the hot electrons, that is, the electrons with high kinetic energy, hop into the third gate insulation layer
206
b
due to the voltage applied to the second control gate RCG
205
, and data is thus written.
Erasing data is accomplished as follows. By applying a specific voltage to the drain region
201
b
and second control gate RCG
205
, a hole is created by the tunnel effect in the neighborhood of the channel formation region of the drain region
201
b
. This hole is a hot hole, that is, a hole trapping high kinetic energy, and jumps into the third gate insulation layer
206
b
. If an electron is trapped at the trap level in the silicon nitride layer (second layer) at this time, the electron and hole couple and die. That is, the charge is depleted and the initial state is restored. This is called the BBH (band-to-band) tunneling hole erasing mechanism, i.e., a method of erasing by band-to-band tunneling.
The initial state is restored as a result of electron-hole bonding as described above, but it is important to note that in order for this to happen the electron and hole must be injected to the same spatial location. This is because the silicon nitride layer is an insulator and the carriers (electron and hole) cannot move through the silicon nitride layer structure and bond again.
Writing with a hot electron occurs near the word gate WG
203
in the split gate memory device shown in FIG.
7
.
Erasing by means of the BBH erase mechanism, however, occurs at the edge of the drain, that is, near the edge part of the drain region
201
b.
In other words, even if the total charge trapped at the trap level in the silicon nitride layer of the device shown in
FIG. 7
is 0, residual positive and negative charges remain stored in a charge trapping region. Furthermore, because a charge causing these charges to cancel each other out is not supplied, they gradually increase through repeated write and erase cycles.
When an unbalanced charge thus remains internally, there is a significant drop in the mutual conductance of the MOS transistors. Furthermore, this is a significant problem with respect to the structure of rewritable memory because this drop in conductance changes as the write and erase cycles repeat.
OBJECTS AND SUMMARY OF THE INVENTION
To solve this problem a nonvolatile memory device according to one aspect of the present invention has first and second impurity regions formed in a substrate with a channel region therebetween; a word gate formed above the channel region with a first gate insulation layer therebetween; a first control gate formed to one side of the word gate with a first side insulation layer therebetween; a second control gate formed to another side of the word gate with a second side insulation layer therebetween; a second gate insulation layer having a charge trapping region formed between the substrate and the first control gate; and a third gate insulation layer having a charge trapping region formed between the substrate and second control gate. With this configuration, the magnitude of an electric field applied in a direction substantially orthogonal relative to the substrate surface between the substrate and first control gate is lower within a first, range in the gate length direction adjacent the first side insulation layer than it is within a second

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