Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1995-05-11
2001-06-12
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S319000, C257S320000
Reexamination Certificate
active
06246088
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices, and in particular, to semiconductor devices having nonvolatile memory structures.
BACKGROUND OF THE INVENTION
A dual-bit nonvolatile memory structure may include three transistors, a first floating gate transistor, a second floating gate transistor, and the other is a select gate transistor. The two floating gate transistors are formed over portions of a common channel region. The floating gates for the two floating gate transistors extend completely across all of the channel region in at least one direction between field isolation regions. The first floating gate transistor is connected to a first bit line, and the second floating gate transistor is connected to a second bit line.
The dual-bit memory structure may have problems related to read disturb. For example, the data in the second floating gate transistor is to be read. The first bit line is grounded and the second bit line at a potential of about one volt. The state of the bit is determined by a sense amplifier that is connected to the second bit line. The control gate of the first floating gate transistor and the select gate are placed at relatively high potentials (about five volts or higher), so that electrons may flow beneath the first floating gate and select gate. The control gate of the second floating gate transistor is grounded during the read operation. Electrons may be injected into the floating gate of the first floating gate transistor while the second floating gate transistor is read. In other words, electrons within the channel under the first floating gate transistor may be pulled into the floating gate by the high potential on the control gate of the first floating gate transistor. If the first floating gate transistor is programmed to have a threshold voltage −2 volts, the reading of the second floating gate transistor typically will increase the threshold voltage of the first floating gate transistor as electrons are injected into the floating gate of the first floating gate transistor. Data in the first floating gate transistor may not be determined by a sense amplifier because it is at a state between being programmed and erased, or the data may be inverted, in which case the data in the floating gate does not correspond to the data originally programmed into it. Data disturb problems in any type of memory cell are undesired.
SUMMARY OF THE INVENTION
The present invention includes a nonvolatile memory circuit, a nonvolatile memory structure, and the process for forming the structure. The nonvolatile memory circuit is for storing a plurality of bits of data and comprises first, second, third, fourth, and fifth transistors. The first transistor has a gate, a first source/drain, and a second source/drain, and the second transistor has a control gate, a floating gate, a first source/drain, and a second source/drain. The first source/drains of the first and second transistors are coupled to each other, and the gate of the first transistor and the control gate of the second transistor are coupled to each other. The third transistor has a gate, a first source/drain, and a second source/drain. The second source/drain regions of the first and second transistors and the first source/drain region of the third transistor are coupled to each other. The fourth transistor has a control gate, a floating gate, a first source/drain, and a second source/drain, and the fifth transistor has a gate, a first source/drain, and a second source/drain. The first source/drains of the fourth and fifth transistors are coupled to each other. The second source/drain regions of the third, fourth and fifth transistors are coupled to one another. The control gate of the fourth transistor and the gate of the fifth transistor are coupled to each other.
The present invention may also include a nonvolatile memory structure for storing a plurality of bits of data that comprises a semiconductor substrate, a first doped region and a second doped region, a channel region, a first gate dielectric layer, a first floating gate and a second floating gate, an intergate dielectric layer, a first conductive member and a second conductive member, and a third conductive member. The semiconductor substrate has a first conductivity type. The first and second doped regions lie within the substrate and are spaced apart from each other. The channel region lies within the substrate and between the first and second doped regions. The first gate dielectric layer and the first and second floating gates overlie the substrate. The first and second floating gates are spaced-apart from each other and do not extend across all of the channel region in any direction. The intergate dielectric layer overlies the first and second floating gates. The first conductive member lies adjacent to the first floating gate and overlies a first portion of the channel region that is not covered by the first or second floating gates. The second conductive member lies adjacent to the second floating gate and overlies a second portion of the channel region that is not covered by the first or second floating gates. The first and second conductive members are spaced apart from each other. The third conductive member overlies a third portion of the channel region that lies between the first and second conductive members. The present invention also includes a process for forming the memory structure.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
REFERENCES:
patent: 5194925 (1993-03-01), Ajika et al.
patent: 5225362 (1993-07-01), Bergemont
patent: 5268319 (1993-12-01), Harari
patent: 5278087 (1994-01-01), Jenq
patent: 5278439 (1994-01-01), Ma et al.
Eckert II George C.
Lee Eddie
Meyer George R.
Motorola Inc.
Rodriguez Robert A.
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