Nonvolatile memory cells having split gate structure and...

Details Nonvolatile memory cells having split gate structure and... Nonvolatile memory cells having split gate structure and...

2003-03-28

2004-06-22

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000

Reexamination Certificate

active

06753571

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2002-17090, filed on Mar. 28, 2002, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, generally, to semiconductor devices and methods of fabricating the same. More specifically, the present invention is directed to nonvolatile memory cells having a split gate structure and methods of fabricating nonvolatile memory cells having a split gate structure.
2. Discussion of Related Art
Semiconductor memory devices for storing data can be typically categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when their power supply is interrupted, and nonvolatile memory devices retain their stored data even when their power supply is interrupted. Accordingly, the nonvolatile memory devices have been widely used in memory cards, mobile telecommunication systems or the like.
The nonvolatile memory devices may have either stacked gate structural cells or split gate structural cells. The split gate structural cells require less power for program operation or erase operation then stacked gate structural cells.
FIG. 1
is a top plan view of a conventional split gate structural cell.
FIGS. 2A
,
3
,
4
,
5
A, and
6
A are cross-sectional views taken along the line I—I of
FIG. 1
, and
FIGS. 3B
,
5
B, and
6
B are cross-sectional views taken along the line II—II of FIG.
1
.
Referring to
FIGS. 1
,
2
A, and
2
B, a tunnel oxide layer
3
and a floating gate layer
5
are sequentially formed on a semiconductor substrate
1
. The floating gate layer
5
is formed of a doped polysilicon layer. The floating gate layer
5
, the tunnel oxide layer
3
, and the semiconductor substrate
1
are patterned to form a trench region defining an active region
7
a
at a predetermined region of the semiconductor substrate
1
. As a result, the active region
7
a
is covered with the tunnel oxide layer
3
and the floating gate layer
5
. A nitride layer pattern
9
is formed on the semiconductor substrate having the device isolation layer
7
. The nitride layer pattern
9
has an opening
9
a
crossing the active region.
Referring to
FIGS. 1 and 3
, oxide layer spacers
11
are formed on sidewalls of the opening
9
a
. The floating gate layer
5
exposed in the opening
9
a
is etched using the oxide layer spacers
11
and the nitride layer pattern
9
as etch masks, to expose the tunnel oxide layer
3
formed on the active region
7
a
. Impurity ions are then selectively implanted into a surface of the semiconductor substrate under the exposed tunnel oxide layer
3
, thereby forming a source region
13
.
Referring to
FIGS. 1 and 4
, the semiconductor substrate having the source region
13
is thermally oxidized to form a sidewall oxide layer on sidewalls of the patterned floating gate layer
5
. The sidewall oxide layer (not shown) and the tunnel oxide layer
3
are successively etched using an anisotropic etch process to expose the source region
13
and to simultaneously leave a sidewall oxide layer pattern
15
covering the sidewall of the patterned floating gate layer
5
. A doped polysilicon layer is formed on an entire surface of the semiconductor substrate, the sidewall oxide layer pattern
15
, and filling the void left from the anisotropic etch. The doped polysilicon layer is etched back until a top surface of the nitride layer pattern
9
is exposed, thereby forming a common source line
17
crossing the active region
7
a
on the exposed source region
13
.
Referring to
FIGS. 1
,
5
A, and
5
B, the exposed nitride layer pattern
9
, as shown in
FIG. 4
, is selectively removed to expose the floating gate layer
5
thereunder. Thereafter, the exposed floating gate layer
5
and the tunnel oxide layer
3
are successively etched using the spacers
11
as etch masks, to expose the active region. As a result, as illustrated in
FIG. 5A
, floating gates
5
a
are formed between the spacers
11
and the active region
7
a
. Here, in the event that the floating gate layer
5
and the common source line
17
are formed of a polysilicon layer, the common source line
17
may be also etched while etching the floating gate layer
5
. Therefore, a thickness of the floating gate layer
5
should be reduced in order to prevent the common source line
17
from being over-etched.
The semiconductor substrate having the floating gates
5
a
is thermally oxidized to form a gate oxide layer
19
on the exposed active region. The common source line
17
and the floating gates
5
a
are also thermally oxidized during formation of the gate oxide layer
19
. Thus, the gate oxide layer
19
is formed substantially even with the top surface of the floating gates
5
a
. Alternatively, the gate oxide layer
19
may be formed substantially even with the top surface of the common source line
17
. A gate conductive layer
21
is formed on an entire surface of the semiconductor substrate where the gate oxide layer
19
is formed.
Referring to
FIGS. 1
,
6
A, and
6
B, the gate conductive layer
21
is anisotropically etched to form gate electrodes
21
a
on the vertical sidewalls of the spacers
11
and the top surface of the gate oxide layer
19
. The gate electrodes
21
a
, as illustrated in
FIG. 1
, cross over the active region and act as word lines. Using the gate electrodes
21
a
, the spacers
11
, and the common source line
17
as ion implantation masks, impurity ions are implanted into the active region to form drain regions
23
. An interlayer dielectric layer (ILD)
25
is formed on an entire surface of the semiconductor substrate having the drain regions
23
. The ILD
25
is patterned to form bit line contact holes
27
exposing the drain regions
23
. Next, a bit line
29
is formed to cover the bit line contact holes
27
, which are parallel with the active region.
The foregoing conventional nonvolatile memory cell is programmed by applying a ground voltage to the bit line
29
, applying a program voltage to the common source line
17
, and applying a voltage higher than a threshold voltage to the gate electrode
21
a
. In more detail, if a program voltage is applied to the common source line
17
, an inversion layer, e.g., a first channel is formed at a surface of the semiconductor substrate
1
under the floating gate
5
a
. This is because a program voltage applied to the common source line
17
induces a sufficient voltage for forming the first channel to the floating gate
5
a
. Also, a second channel is formed at the surface of the semiconductor substrate I under the gate electrode
21
a
. Thus, a strong lateral electric field is formed between the first and second channels, and hot electrons are generated by the lateral electric field.
The hot electrons are injected into the floating gate
5
a
through the tunnel oxide layer
3
. This operation is performed due to a vertical electric field, which is built by a voltage induced to the floating gate
5
a
. Here, the vertical electric field should be increased in order to improve program efficiency. The vertical electric field is proportional to a coupling ratio of the memory cell, and the coupling ratio has a direct relationship to an overlapped area between the common source line
17
and the floating gate
5
a
and/or an overlapped area between the source region
13
and the floating gate
5
a
. Thus, it is required to increase a lateral diffusion of the source region
13
or increase a thickness of the floating gate
5
a
in order to improve the program efficiency. However, when the thickness of the floating gate
5
a
is increased, as illustrated in
FIG. 5A
, the common source line
17
may be over-etched. In addition, if a lateral diffusion of the source region
13
is increased, a punch through phenomenon may occur during a read mode of the nonvolatile memory cell.
SUMMARY OF THE INVENTION
It is therefore a feature of the present invention to provide nonvolatile m

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