Nonvolatile memory cell with a nitridated oxide layer

Details Nonvolatile memory cell with a nitridated oxide layer Nonvolatile memory cell with a nitridated oxide layer

2002-07-19

2004-06-15

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S257000, C438S260000, C438S261000, C438S778000, C438S783000, C438S791000

Reexamination Certificate

active

06750157

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to a method for fabricating a memory cell device which exhibits improved retention characteristics.
BACKGROUND ART
Memory devices for non-volatile storage of information are currently in widespread use today in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in place, flash memory is less expensive and denser. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. However, the bottom oxide layer of the multilayer ONO insulator has a tendency to allow charge stored in the nitride layer of the multilayer ONO to leak. This results in severe difficulties in programming, reading and erasing the memory cell. As scaling down of memory cell devices continues, the need to form thinner ONO dielectric layers without compromising programming and erasure abilities of the device increases. In conventional EEPROM devices, a phosphorous doped N+ polysilicon gate may be employed as the polysilicon control gate. However, the use of a N+ polysilicon gate limits the minimum thickness of the bottom oxide layer to be greater than 50 angstroms. This is because a thickness less than 50 angstroms would lead to direct tunneling of charge stored in the middle nitride layer down into the bottom oxide layer. Accordingly, the use of a N+ polysilicon gate can cause problems in memory cell fabrication because it can hinder the ability to reduce the thickness of the ONO gate stack material.
The control gate is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bit line. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a single column is connected to the same bit line. In addition, each flash cell has its stacked gate terminal connected to a different word line, while all the flash cells in the array have their source terminals connected to a common source terminal. In operation, individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Such a single bit stacked gate flash memory cell is programmed by applying a voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomena called “Fowler-Nordheim” tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, an electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
In conventional single bit flash memory devices, an erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells which fail the initial verification. Thereafter, the erased status of the cell is again verified, and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
Recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell. The conventional programming and erase verification methods employed with single bit stacked gate architectures are not adequate for such dual bit devices. Recently, dual bit flash memory structures have been introduced that do not utilize a floating gate, such as an ONO flash memory device that employs a polysilicon layer over the ONO layer for providing wordline connections. Conventional fabrication techniques do not address the characteristics associated with these types of devices. Therefore, there is an unmet need in the art for improved data retention in a scaled down dual bit memory architecture.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
A novel memory cell structure and a methodology are provided for fabricating a memory cell, such as a nonvolatile memory, operating in dual bit mode. The present invention facilitates optimizing the performance of the memory cell such as improving asymmetrical programming and reading of the memory cell by improving the retention of charges within discreet layers/locations of the memory cell structure.
More specifically, optimizing the performance of the memory cell may be accomplished in part by using a P+ polysilicon gate as opposed to a conventional N+ polysilicon gate. Unlike phosphorous doped N+ polysilicon gates, the P+ polysilicon gate facili

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