Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2000-06-12
2001-03-13
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S052000, C365S185050
Reexamination Certificate
active
06201725
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention pertains to the field of semiconductor memory devices, and more particularly, to a nonvolatile memory cell produced of semiconductor transistor structures common to semiconductor logic devices.
2) Background of the Related Art
Semiconductor memory devices may be largely divided into Random Access Memories (RAMs) and Read Only Memories (ROMs). RAMs, also referred to as volatile memories because the stored data is destroyed with the passage of time upon removal of the power supply, allow rapid data storage and data retrieval. ROMS, also referred to as nonvolatile memories because they retain data once it is entered, typically have slower data storage and data retrieval times.
One popular type of ROM is the Electrically Erasable Programmable Read Only Memory (EEPROM) in which data is electrically programmed and erased. A flash EEPROM, which is electrically erasable at high speed without being removed from a circuit board, offers the advantages of a simple memory cell structure, cheap cost, and no need for a refresh signal to retain the data.
EEPROM cells are largely divided into two types: a NOR type EEPROM and a NAND type EEPROM.
FIG. 1
shows a circuit diagram for a NOR-type flash EEPROM cell
100
. A metal oxide semiconductor (MOS) transistor
120
is provided with a floating gate
110
and a control gate
160
. The floating gate
110
may be programmed with a charge according to the data to be stored in the memory cell
100
. Data is read by selecting the transistor on a word line connected to the control gate
160
and detecting the presence or absence of a current through the transistor on a bit line
170
connected to one terminal of the device.
A number of different memory cell structures have been used for a nonvolatile memory device.
FIG. 2
shows one configuration of a NOR-type Flash EEPROM cell
200
according to the prior art. The memory cell
200
comprises a semiconductor substrate
205
having first and second impurity regions
225
and
235
formed in a top surface of a well
202
. The first impurity region
225
is connected with a bit line
270
of the memory device
200
, while the second impurity region
235
is connected with ground potential. A first oxide later
230
is deposited on the top surface of the semiconductor substrate where the first and second impurity regions
225
and
235
are formed.
A floating gate
210
is formed on the first oxide layer
230
above and between the first and second impurity regions
225
and
235
. A control gate
260
is also formed above and between the first and second impurity regions
225
and
235
. A portion of the control gate
260
is formed above the floating gate
210
, separated by a second oxide layer
250
. The floating gate
210
and the control gate
260
may each be formed of conductive polysilicon layers.
To program the EEPROM device
200
with a potential V
p
, the word line connected with the control gate
260
is supplied with a large positive potential V
PGM
(e.g., V
PGM
=12.5 Volts). This causes an injection of electrons onto the floating gate
210
. To read the data from the cell
200
, a lower positive voltage V
cc
, (e.g., 5 volts) is applied to the control gate while the bit line is supplied with a smaller positive voltage (e.g., 1-2 volts). Data
0
or
1
is read from the cell
200
according to the presence or absence of a current path through the cell, relying on the principle that the threshold voltage V
th
of the cell is changed to a voltage greater than +5V when electrons are stored in the cell, while the threshold voltage V
th
is about 1.5V when electrons are not stored on the floating gate. Data may be erased though exposure to ultraviolet light radiation, or through a separate erase gate (not shown).
Disadvantageously, these prior art nonvolatile memory cell structures are not readily adaptable to integration in a logic device such as a gate array. For example, the EEPROM cell
200
requires two polysilicon layers or more, whereas the typical gate array process uses a single polysilicon process. Yet, it is desirable to provide nonvolatile memory cells in a gate array device.
Accordingly, it would be advantageous to provide a nonvolatile memory cell which may be easily integrated into a semiconductor logic device. It would also be advantageous to provide a nonvolatile memory cell which may be easily integrated into a gate array logic device. It would be further advantageous to provide a nonvolatile memory cell which can use the same process technologies and array structures which are used to manufacture gate array logic circuitry. Other and further objects and advantages will appear hereinafter.
SUMMARY OF THE INVENTION
The present invention comprises a nonvolatile memory cell constructed from MOS transistor structures.
In one aspect of the invention, a nonvolatile memory call includes first and second MOS transistors. A gate of the first transistor is a control gate while a gate of the other transistor is a floating gate. In a preferred embodiment, the nonvolatile memory cell includes a PMOS transistor and an NMOS transistor in a CMOS cell.
In another aspect of the invention, a nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array.
In another aspect of the present invention, a nonvolatile memory cell may be fabricated in a logic device with the standard processes normally used to produce such a logic device.
REFERENCES:
patent: 5338969 (1994-08-01), Kaya
patent: 6052301 (2000-04-01), Ikeda et al.
patent: 6108242 (2000-08-01), Lin et al.
patent: 6115288 (2000-09-01), Amanai et al.
Chien Chung-Jen
Yao Chingchi
Dinh Son T.
Jones Volentine, L.L.C.
Oki Semiconductor
LandOfFree
Nonvolatile memory cell structure for integration with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nonvolatile memory cell structure for integration with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nonvolatile memory cell structure for integration with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2518348