Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-10-16
2007-10-16
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S185090, C365S189050
Reexamination Certificate
active
11159303
ABSTRACT:
A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.
REFERENCES:
patent: 6421274 (2002-07-01), Yoshimura
patent: 6639843 (2003-10-01), Miyauchi
patent: 6819608 (2004-11-01), Watanabe
patent: 2004-55100 (2004-02-01), None
Kozakai Kenji
Nakajima Tsutomu
Noda Satoshi
Tokairin Atsushi
Miles & Stockbridge P.C.
Nguyen Van-Thu
Renesas Technology Corp.
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