Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-20
2004-04-20
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000
Reexamination Certificate
active
06724037
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. In particular, the present invention relates to an electrically erasable and programmable read only memory (hereinafter, referred to as an “EEPROM”). More specifically, the present invention relates a nonvolatile semiconductor memory using a multi-valued technique. The present invention is effective for a nonvolatile semiconductor memory with a channel length of 0.01 to 1 &mgr;m (preferably, 0.01 to 0.5 &mgr;m). Furthermore, the present invention relates to a semiconductor device having a nonvolatile semiconductor memory.
In this specification, the EEPROM refers to all the electrically erasable and programmable read only memories, and includes, for example, a full-function EEPROM and a flash memory. Furthermore, unless otherwise specified, the terms “nonvolatile memory” and “nonvolatile semiconductor memory” and the term “EEPROM” are used interchangeably. Furthermore, a semiconductor device refers to all the devices that function by utilizing semiconductor characteristics, and include, for example, electro-optical devices such as a microprocessor, a liquid crystal display device and an EL display device, and electronic apparatus provided with a microprocessor or an electro-optical device.
2. Description of the Related Art
The EEPROM is known as a memory such as a nonvolatile semiconductor memory. Since the EEPROM is a nonvolatile memory, unlike other semiconductor memories, i.e., a dynamic random access memory (DRAM) and a static RAM (SRAM), data are not lost even when a power source is turned off. Furthermore, compared with another nonvolatile memory, i.e., a magnetic disk, the EEPROM has excellent features in terms of an integration density, shock resistance, power consumption, a write/read speed, and the like. Because of these features, there is a tendency that the EEPROM is used as an alternative to various memories such as a magnetic disk and a DRAM.
In particular, the integration density of the EEPROM is being remarkably enhanced. More specifically, the integration density thereof is being increased at a very high pace (i.e., about twice per year). It is expected that the mass-production of the EEPROM with a gigabit capacity will be realized in the near future. Accordingly, the EEPROM will overtake the DRAM in terms of an integration density. Examples of a technique for such enhancement of an integration density include improvement of a circuit configuration, a fine processing technique, and a multi-valued technique.
Regarding the circuit configuration, a full-function EEPROM with a structure of 2 transistors/cell has been improved to a flash memory with a structure of 1 transistor/cell. Furthermore, a NOR-type flash memory requiring a cell area of 10 F
2
(F is a minimum processing size) has been improved to a NAND-type flash memory realizing a cell area of 5 F
2
.
The fine processing technique is the most important technique for promoting a high integration density, miniaturization, and a low cost in substantially all the semiconductors such as an IC, an LSI, a VLSI, and a ULSI. In the EEPROM, a fine processing technique is always introduced in the same way as in the other ICs and the like, and is being developed in accordance with the scaling law.
Furthermore, as a method for enhancing the integration density of a memory, a multi-valued technique is recently being paid attention to. The multi-valued technique refers to a technique for retaining data with three or more values per memory cell. Conventionally, a method for controlling a charge accumulation amount of a floating gate to distinguish three or more states from each other has been developed. A flash memory with four values have already been produced.
As described above, in the EEPROM, remarkable enhancement of an integration density has been achieved by the circuit configuration, the fine processing technique, and the multi-valued technique. In order to further enhance an integration density, it is considered that the fine processing technique and the multi-valued technique are becoming more and more important. However, there are a number of problems in the fine processing technique and the multi-valued technique.
Regarding the fine processing, a scaling limit of the EEPROM is considered to be 0.12 to 0.15 &mgr;m. There are some factors that determine the scaling limit. Examples thereof include a fine processing limit, a short channel effect, and reliability of a tunnel oxide film. Particularly, in an EEPROM requiring an operating voltage higher than that of an ordinary transistor, the short channel effect is a serious problem, and even though fine processing is possible, the EEPROM may not function as a memory due to the short channel effect.
The short channel effect collectively refers to various phenomena that occur in the case where the channel length of a transistor is shortened. Examples of the phenomena include a punchthrough phenomenon, degradation of subthreshold characteristics (increase in an S value), and a decrease in a threshold voltage. The short channel effect is mostly caused by a depletion layer region spreading from a drain region. Thus, it is a problem how to suppress the spread of a depletion layer region.
Furthermore, regarding the multi-valued technique, in the case of using a conventional method for controlling a charge accumulation amount of a floating gate electrode, it is considered to be difficult to realize the control of variation in a charge accumulation amount, satisfactory charge retention characteristics, and satisfactory read characteristics. Although a flash memory with four values has been realized by the conventional method, in order to further enhance the multi-valued technique, the development of a multi-valued technique different from the conventional method is considered to be required.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above, and it is an object of the present invention to effectively suppress a short channel effect that occurs due to fine processing, and to allow a cell to have multi values by a method completely different from a multi-valued technique according to a conventional method for controlling a charge accumulation amount of a floating gate electrode. It is another object of the present invention to provide a nonvolatile memory with a very high integration density.
According to the present invention, in order to suppress a short channel effect caused by fine processing, a plurality of local impurity regions are formed in an active region of a memory transistor. More specifically, impurity regions are formed in a stripe shape in a channel length direction. Impurities having conductivity reverse to that of the impurities used for source and drain regions are used for the impurity regions provided in a stripe shape.
In this specification, a region surrounded by a source region, a drain region, and an element isolation region is referred to as an “active region”, and the active region is further separated into impurity regions provided in a stripe shape and channel forming regions.
The present invention is intended to be applied to a fine nonvolatile memory. More specifically, the present invention is effective for a nonvolatile semiconductor memory having a channel length of 0.01 to 1 &mgr;m (preferably, 0.01 to 0.5 &mgr;m), a width of an impurity region of 0.01 to 1 &mgr;m (preferably, 0.01 to 0.5 &mgr;m), and a width of a channel forming region of 0.01 to 1 &mgr;m (preferably, 0.01 to 0.5 &mgr;m).
In a fine transistor, a procedure for providing local impurity regions in an active region is disclosed in Japanese Patent Application Laid-open No. Hei 10-65162. In this publication, it is described that by providing local impurity regions in an active region, the spread of a depletion layer from a drain region can be suppressed, and a short channel effect can be suppressed while a high ON current is maintained.
In the above-mentioned publication, since the effect of suppressing a depletion layer is ta
Kato Kiyoshi
Koyama Jun
Yamazaki Shunpei
Costellia Jeffrey L.
Nixon & Peabody LLP
Quinto Kevin
Semiconductor Energy Laboratory Co,. Ltd.
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