Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-07-04
2006-07-04
Mai, Son (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185130, C365S185170
Reexamination Certificate
active
07072225
ABSTRACT:
There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.
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Kanamitsu Michitaro
Kubono Shoji
Kurata Hideaki
Nozoe Atsushi
Takase Yoshinori
Hitachi ULSI Systems Co. Ltd.
Mai Son
Miles & Stockbridge PC
Renesas Technology Corp.
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